Direct Bonding Considerations

Direct bonding is challenging because of the requirement of having smooth and contaminant free surfaces. Even if a micron level particle is present (e.g. contamination), it may lead to a void creation or prevent bonding at the interface. In standard fabrication, smoothness is quantified through root-mean-square (RMS) roughness by scanning with an atomic force microscope. A typical virgin prime silicon or SOI wafer that is polished by the manufacturer will have a surface roughness of 3~7 ÅRMS. If the same wafer undergoes thermal oxide growth in a furnace, the roughness typically stays the same. In most literature, wafer bonding is stated to require a surface roughness of 5~10 ÅRMS [7.6]~[7.9].

7.2.1 Surface Roughness and Nanopillars

Sometimes even when a wafer is thoroughly cleaned, contamination could be introduced during deposition. As an example, we had deposited and attempted to bond a pair of identical wafers with 400-nm-thick, PECVD silicon-rich nitride film that has a roughness of 10 ÅRMS. These nitride wafers debonded immediately even though spontaneous bonding should have occurred given the roughness requirement. It was eventually observed that a few micron-sized contaminating particles were constantly present after the deposition. This is because PECVD is inherently subject to contamination due to the strong electric field within the chamber that can attract charged particles that were settling on the electrode or chamber wall and redeposit them onto the cleaned wafer [7.26][7.27].

Even without contamination, the topography of the deposition film can prevent bonding.

As an example, we had deposited a 500-nm LPCVD nitride thin film (Tytan 4600 Mini Fourstack Horizontal Furnace, TYSTAR) and the roughness was measured to be ≤ 10 ÅRMS.

After the wafer bonding step, the wafers debonded immediately prior to annealing. A further AFM study showed that 10-nm tall nanopillars were scattered throughout a scan area. When a 200-nm thick silicon rich nitride film was deposited and scanned (see Figure 7-1), the nanopillars are still scarce and short enough such that the nitride wafers can still bond [7.28]~[7.30]. With the same deposition conditions but at 600-nm thick the roughness increased from 7 to 10 ÅRMS.

More importantly, the distribution and size of the nanopillars increase drastically as shown in Figure 7-1. Both the size and frequency of the nanopillars can significant reduce the bonding

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contact area. This explains why, without CMP, it is extremely difficult to bond thicker nitride films even though there is no significant increase in roughness over thinner films.

Figure 7-1: The AFM scan shows a surface roughness of < 10 ÅRMS which is acceptable for achieving spontaneous bond. There are very few 10-nm nanopillars but at this thickness it is still bondable.

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Figure 7-2: Although RMS roughness did not increase significantly at 600-nm thick deposition, the pillars are much more noticeable in size and frequency. These large pillars are attributed to bonding failures of thicker

nitride films.

In addition to surface smoothness and flatness, the surface oxide seems to play an important role. Though this concept still requires much investigation, several groups have correlated the mechanism. Usenko and Senawiratne managed to bond nitride to oxide after converting the top silicon nitride layer into silicon oxynitride [7.17]. Reck et al. have noticed a higher bonding strength when two wafers with thin nitride films are purposely oxidized compared to films that are BHF treated [7.29]. Although not mentioned, this phenomenon can be seen in the void-free direct bonding of CMUT array fabricated by Christensen et al. as they bonded two silicon oxide wafers [7.31].

7.2.2 Problem with Current SOIs

The standard wafer bonding process for CMUTs employs SOIs, which are created with traditional wafer bonding techniques where a thin silicon wafer is bonded to a bottom thermal oxide wafer. The backside of the silicon wafer is then grinded and polished with a CMP to achieve a thin and ultra smooth device layer. A problem arises in this polishing process as CMUT fabrication requires a device layer that ranges from several hundred nanometers to less

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than 3-µm thick. The device layer's thickness uniformity is usually very poor due to the rotational polishing nature of CMP. Ultrasil, one of the world's largest SOI providers specifies an intra-wafer minimum thickness variation of ± 0.5 µm, which is far from ideal. As an example, medical imaging CMUTs typically have a membrane thickness of around 0.5~2 µm and a cavity diameter of 30~60 µm. A minimum thickness variation of ±0.5 µm could mean that within the same batch of CMUTs, some could be 1-MHz higher in resonant frequency than the other while some membranes could be too thin and collapse. Most often, CMUT geometries are designed such that the performance is compromised in order to accommodate the thickness variation. This issue was originally not a problem for researchers until companies like Soitec discontinued SIMOX-based technology for smaller (4”~6”) wafers that can guarantee thin (< 1 µm) and ultra uniform (< 5 %) SOI wafers.

7.2.3 Good Practices for Silicon-to-Oxide Bonding

Since the cleanliness of the wafers is paramount to bonding, utmost care must be taken prior to bonding. There are some minor variations among CMUT academic groups on wafer cleaning.

Huang et al. reported using a 4:1 Piranha for 20 minutes, followed by a 50:1 HF 15-seconds dip, then a RCA-1 treatment for 5 minutes [7.11]. Logan et al. reported using a standard RCA-1 and RCA-2 bath, a low power oxygen plasma descum, followed by another RCA 1 [7.14]. Given that metallic contamination should not be present in the early process and only virgin prime wafers were used, our group uses RCA 1 cleaning for 5 minutes followed by 5 minutes of continuous rinsing with DI water. In most cases, the likely cause of voids is the environment exposure between RCA cleaning and bonding. Even drying with a nitrogen gun at the bench could introduce micron level particulate to land. In our group, the wafers are immediately spin dried at high speed (one can use a standard spinner) after the DI-water rinse, then sealed in a thoroughly cleaned wafer holder to reduce exposure to air particulate. The bonding chamber (AWB 04, AML) is pre-cleaned by a thorough IPA wipe. Wafers are then carefully and swiftly secured in the chamber with visual inspection to ensure that no dust has landed on the wafer (one must wear a mask). Once the lid is closed, an in-situ radical activation (i.e. oxygen plasma) was activated for 15 minute followed by bonding at 3000-kN of force in 0.8-µBar high vacuum at room temperature. The plasma is used to promote surface silanol groups which increase bonding strength without increasing surface roughness [7.32]. Bonding yield has been consistently above 90% (i.e. one or two voids with 1-cm diameter) since these guidelines were followed.

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