Bi-directional Tracks

The routing of signal paths can be eased by bi-directional tracks, that can propagate a signal in both directions of a line as opposed to unidirectional wiring. In physical FP- GAs bi-directional tracks are realized using two anti-parallel tristate buffers driving the same wire as shown in Figure 4.9a. On the other hand, the study in [60] shows that uni- directional single-driver wiring as shown in Figure 4.9b can reduce area and delay, since regular buffers require less transistors than tristate buffers and also the load capacitance is reduced. For the V-FPGA both techniques are considered.

While unidirectional wiring is a trivial matter, unfortunately bidirectional wires are nat- urally not possible with virtual FPGAs because the signal flow of configured underly- ing resources is always directional (except for the device I/Os that incorporate tristate buffers). A bi-directional track must therefore be modeled by two uni-directional wires. The propagation of a signal in both directions and the sharing of the track by a plurality of potential sources (e.g. 2 PSMs and 1 CLB) can then be implemented, for example, by an arrangement as shown in Figure 4.10, which enables the emulation of tristate signals by additional AND gates. However, since in virtual architectures the efficient use of un- derlying resources matters, another technique has been developed for the V-FPGA that uses less resources and is presented in Section 4.1.4.1. The pleasant specialty is that it allows the emulation of bi-directional wiring without additional resources. Furthermore, without modifications it can be used as uni-directional and as bi-directional track.

CLB CLB

(a) Bi-directional wiring

CLB CLB

(b) Uni-directional wiring

Figure 4.9.: Routing tracks using (a) bi-directional or (b) uni-directional wiring [60]

Din Dout en Din Dout en Din Dout en Din Dout en

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1

4.1. 2D Generic Architecture

4.1.4.1. Loopback Propagation

Defining a track as a pair of two oppositely directed wires, the idea behind the presented technique, hereinafter called Loopback Propagation, is to feed a signal (e.g. from an output of a CLB) only into one of the two wires of a track and at the end of the track to replicate the signal onto the opposite direction. An example is depicted in Figure 4.11, where a signal on a wire in right-to-left direction can be replicated by a MUX in the PSM onto a wire in left-to-right direction as highlighted in red colour, carrying the signal in two directions simultaneously. Thereby the rules defined in the following must be obeyed:

1. Read and write accesses by connection boxes on a track occur on different wires, i.e. CBws write (drive wires) only in one direction, while CBrs read from the opposite wires that carry the replicated signals.

2. The definition, in which direction the original signal is written and from which di- rection the replicated signal is read, must be applied globally to all tracks, e.g.:

a) In horizontal tracks, always write on lines leading from right to left, and read from lines leading from left to right.

b) In vertical tracks, always write on lines leading from top to bottom, and read from lines leading from bottom to top.

3. The idle value of unused wires must be ’1’.

4. [A track is not driven by two sources simultaneously].

While the first three rules are strict, the last one depends on the capabilities of the CAD tools with respect to the routing steps. In case that the CAD tools support multimode tracks (i.e. a track with two wires can be seen either as one bi-directional track or as two separate uni-directional tracks), then the last rule may be violated in favour of a more ef- ficient routing, allowing one wire of a track to be driven by a CBw and the opposite wire to be driven by an independent signal through the PSM that has been routed to the same track. 1 1 1 1 1 1 1 1 config unit nRST clk 1 1 1 1 1 1 1 1 config unit m2 CBr CBw 1 0 0 0 00

1 1 1 1 1 1 1 1 config unit LUT configuration unit DQ nQ nRST clk 1 nRST clk SOMInSS

lut15..lut0ffenrren rr1 rr0tren tr1 tr0lren lr1 lr0bren br1 br0w3..w0

SCLK 1 1 1 1 1 1 1 1 config unit D-FF m1 m2 CLB 1 1 1 1 1 1 1 1 config unit 1 1 1 1 1 1 1 1 config unit nRST clk m2 (a) Path A 1 1 1 1 1 1 1 1 config unit LUT configuration unit DQ nQ nRST clk 1 nRST clk SOMInSS

lut15..lut0ffenrren rr1 rr0tren tr1 tr0lren lr1 lr0bren br1 br0w3..w0

SCLK 1 1 1 1 1 1 1 1 config unit D-FF m1 m2 CLB 1 1 1 1 1 1 1 1 config unit 1 1 1 1 1 1 1 1 config unit nRST clk m2 (b) Path B

Figure 4.12.: Connection between two CLBs through two different paths

As it can be seen in Figure 4.11, the ability to replicate a signal comes at no extra costs as the employed 4:1 MUXs in the PSMs are anyway needed for the routing. The difference is that on the right side and on the top side of a PSM the first position of a MUX selects not the idle value ’1’ but the incoming signal of the corresponding track, thus forming a loopback. Without Loopback Propagation the first position would be reserved for the idle value ’1’ which is selected when a track is unused. With Loopback Propagation the idle value of an unused track in right-to-left (or top-to-bottom) direction is replicated in left-to-right (or bottom-to-top) direction, thus having equivalent functionality for the idle case plus extending the functionality of normal operation by bi-directionality without additional resources. Compared to the version in [50] it saves 2W AND gates per PSM and compared to the tri-state emulation in [54] it saves W AND-gates per CLB-input and substitutes 2W AND-gates + W OR-gates by W MUX2 per CLB-output. The disadvantage of Loopback Propagation is that replicated signals have an additional delay since they need to pass through another MUX. This leads to asymmetric propagation delays depending on the direction of signal flow. For instance, Figure 4.12a and Figure 4.12b show two different paths for connecting two CLBs traversing the same number of routing channels, whereby path B has a longer delay than path A because it relies on signal replication to change the direction. CAD tools need either to be aware about this peculiarity by considering different wire models for different directions or alternatively one common worst case wire model (representing the loopback case) needs to be applied for all directions.

4.1. 2D Generic Architecture