Dynamic Logic Circuits

The basic idea behind the dynamic logic is to use the capacitive input of the MOSFET to store a charge and thus remember a logic level for later use. The output decays with time unless it is refreshed periodically since it is stored in a capacitor. Dynamic logic gates, which are also known as clocked logic gates, are used to decrease complexity, increase speed, and lower power dissipation.

Figure 2.17 shows the basic structure of a dynamic CMOS logic circuit. The dynamic logic design eliminates one of the switch networks from a complementary logic circuit, thus reducing the number of transistors required to realize a logic function by almost 50%. The operation of a dynamic circuit has two phases: a precharge phase and an evaluation phase depending on the state of the clock signal. When clock CLK¼0, the PMOS transistor in the circuit is turned ON and the NMOS transistor in the circuit is turned OFF, and the load capacitance is charged to VDD. This is called the precharge phase.

The precharge phase should be long enough for the load capacitance to completely charge to VDD.

During the precharge phase, since the NMOS transistor is turned OFF, no conducting path exists between VDD and ground, thus eliminating static current. The precharging phase ends and the

evaluation phase begins when the clock CLK turns 1. Now the PMOS transistor is turned OFF and

V_DD Z CLK CLK i/ps NMOS pull-down network

Precharge Evaluate Precharge Evaluate

FIGURE 2.17 Basic structure of a dynamic CMOS logic circuitry.

the NMOS transistor is turned ON. Depending on the values of the inputs and the composition of the pull-down network, a conditional path may exist between the output and the ground. If such a path exists, the capacitor discharges and logic low output is obtained. If no such path exists between the output and the ground, the capacitor retains its value and a logic high output is obtained. In the evaluate phase, since the PMOS transistor is turned OFF, no path exists between VDD and ground, thus

eliminating the static current during that phase also.

Figure 2.18a shows the realization of the 2-input NAND gate using dynamic logic. During the precharge phase (CLK¼0), the NMOS transistor is OFF and the PMOS transistor is ON, and the capacitor is precharged to logic 1. During the evaluate phase, if the inputsAandBare both equal to 0, both the transistors in the pull-down network will be OFF, and the output goes into high impedance state and holds the precharged value of logic 1. WhenA¼0 andB¼1, orA¼1 andB¼0, the pull- down network again will be OFF and the output holds the precharged value of logic 1. WhenA¼1 and

B¼1, both transistors in the pull-down network are ON, and the load capacitor discharges through the low resistance path provided by the NMOS pull-down network, and the output will be a logic 0, which is the expected result of a NAND gate. It should be noted that once the capacitor discharges, it cannot be charged until the next precharge phase. Figure 2.18b illustrates the dynamic logic implementation of a 2-input NOR gate. Another example for the dynamic logic realization is given in Fig. 2.18c. This circuit realizes the function Y¼(ABCþD)0, and the operation of this dynamic logic circuitry can also be explained in a manner explained earlier.

2.1.4

Memory Circuits

Semiconductor memory arrays are widely used in many VLSI subsystems, including microprocessors and other digital systems. More than half of the real estate in many state-of-the-art microprocessors is devoted to cache memories, which are essentially memory arrays. Memory circuits belong to different categories; some memories are volatile, i.e., they lose their information when power is switched off, whereas some memories are nonvolatile. Similarly, some memory circuits allow modification of infor- mation, whereas some only allow reading of prewritten information. As shown in Fig. 2.19, memories may be classified into two main categories, Read=Write Memories (RWMs) or Read Only Memories (ROMs). Read=Write Memories or memory circuits that allow reading (retrieving) and writing (modi- fication) of information are more popularly referred to as Random Access Memories or RAMs. (Historically, RAMs were referred to by that name to contrast with non-semiconductor memories such as disks which allow only sequential access. Actually, ROMs also allow random access in the way RAMs do; however, they should not be called RAMs. The advent of new RAM chips such as page mode

VDD VDD _V DD Y Y A A A B B C D Y B CLK CLK CLK (a) (b) (c)

FIGURE 2.18 Dynamic logic implementation of (a) 2-input NAND gate, (b) 2-input NOR gate, and (c) the logic functionY¼(ABCþD)0.

DRAMs and cached DRAMs have rendered RAMs to be strictly not random access memories because latency for random access to any location is not uniform any more.

In contrast to RAMs, ROMs are nonvolatile, i.e., the data stored in them is not lost when power supply is turned off. The contents of the simple ROM cannot be modified. Some ROMs allow erasing and rewriting of the information (typically, the entire information in the whole chip is erased). The ROMs, which are programmed in the factory and are not reprogrammable anymore, are called mask- programmed ROMs, whereas programmable ROMs (PROMs) allow limited reprogramming, and erasable PROMs (EPROMs), electrically erasable PROMs (EEPROMs), and FLASH memories allow erasing and rewriting of the information in the chip. EPROMs allow erasure of the information using ultraviolet light, whereas EEPROMs and FLASH memories allow erasure by electrical means.

Memory chips are typically organized in the form of a matrix of memory cells. For instance, a 32-kbit memory chip can be organized as 256 rows of 128 cells each. Each cell is capable of storing one bit of binary information, a 0 or a 1. Each cell needs two connections to be selected, a row select signal and a column select signal. All the cells in a row are connected to the same row select signal (also called word- line) and all the cells in a column are connected to the same column select signal (also called bit-line). Only cells that get both the row and column selects activated will get selected. Figure 2.20 shows the structure of a typical memory cell array. A 32-kbit memory chip will have 15 address lines, and if the

Semiconductor Memories

Read/Write Memories (Commonly known as Random Access Memories or RAM)

Read Only Memories (ROM)

Static RAM (SRAM)

Dynamic RAM (DRAM)

Mask Programmed ROM

Programmable ROM PROM EPROM EEPROM FLASH

FIGURE 2.19 Different types of semiconductor memories.

N row address bits 2N _row select lines 2M _column select lines R o w d e c o d e r Column decoder M column address bits 2N_*2M memory cells

FIGURE 2.20 Typical memory array organization.

chip is organized as 256 rows or 128 cells, 8 address lines will be connected to the row address decoder and 7 address lines will be connected to the column address decoder.

2.1.4.1 Static RAM Circuits

Static RAMs are static memory circuits in the sense that information can be held indefinitely as long as power supply is on, which is in constrast to DRAMs which need periodic refreshing. A static RAM cell basically consists of a pair of cross-coupled inverters, as shown in Fig. 2.21a. The cross-coupled latch has two possible stable states, which will be interpreted as the two possible values one wants to store in the cell, the ‘‘0’’ and the ‘‘1’’. To read and write the data contained in the cell, some switches are required. Because the two inverters are cross-coupled, the outputs of the two transistors are complementary to each other. Both outputs are brought out as bit line and complementary bit line. Hence, a pair of switches are provided between the 1-bit cell and the complementary bit lines. Figure 2.21b illustrates the structure of a generic MOS static RAM cell, with the two cross-coupled transistors storing the actual data, the two transistors connected to the word line and bit-lines acting as the access switches and two generic loads, which may be active or passive. Figure 2.21c illustrates a case where the loads are resistive, whereas Fig. 2.21d illustrates the case where the loads are PMOS transistors. A resistive load can be realized using undoped polysilicon. Such a resistive load yields compact cell size and is suitable for high density memory arrays; however, one cannot obtain good noise rejection properties and good energy dissipation properties for passive loads. Low values of the load resistor results in better noise margins and output pull-up times; however, high values of the resistor is better to reduce the amount of standby current drawn by each memory cell. The load can also be realized using an active device, which is the approach in the 6-transistor cell in Fig. 2.21d. This 6-transistor configuration, often called the

Bit line C

Bit line C

Bit line C_⬘

Bit line C⬘ Bit line C Bit line C⬘

Bit line C Bit line C⬘

1-bit SRAM

Load Load

Word line

Word line Word line

V_dd V_dd V_dd (a) (c) (d) (b) R R T5 T6 T3 T1 T2 T4

FIGURE 2.21 Different configurations of the SRAM cell: (a) basic two-inverter latch, (b) generic SRAM cell topology, (c) SRAM cell with resistive load, (d) the 6-transistor CMOS SRAM cell.

full CMOS SRAM, has desirable properties of low power dissipation, high switching speed, and good noise margins. The only disadvantage is that it consumes more area than the cell with the resistive load. In Fig. 2.21d, the cross-coupled latch formed by transistors T1 and T2 forms the core of the SRAM cell. This transistor pair can be in one of two stable states, with either T1 in the ON state or T2 in the ON state. These two stable states form the one-bit information that one can store in this transistor pair. When T1 is ON (conducting), and T2 is OFF, a ‘‘0’’ is considered to be stored in the cell. When a ‘‘1’’ is stored, T2 will be conducting and T1 will be OFF. The transistors T3 and T4 are used to perform the read and write operations. These transistors are turned ON only when the word line is activated (selected). When the word line is not selected, the two pass transistors T3 and T4 are OFF and the latch formed by T1 and T2 simply ‘‘holds’’ the bit it contains. Once the memory cell is selected by using the word line, one can perform read and write operations on the cell. In order to write a ‘‘1’’ into the cell, the bit lineC0

must be forced to logic low, which will turn off transistor T1, which leads to a high voltage level at T1’s drain, which turns T2 ON and the voltage level at T2’s drain goes low. In order to write a ‘‘0’’, voltage level at bit lineCis forced low, forcing T2 to turn off and T1 to turn ON. To accomplish forcing the bit- lines to logic low, a write circuitry has to be used. Figure 2.22 illustrates a static RAM cell complete with read and write circuitry [6]. The write circuitry consists of transistors WT1 and WT2 that are used to forceCorC0to low-voltage appropriately (Table 2.1). Typically, two NOR gates are used to generate the appropriate gate signals for the transistors WT1 and WT2 (not shown in Fig. 2.22).

The read circuitry is also illustrated in Fig. 2.22. In order to read values contained in a cell, the cell is selected using the word select line. Both transistors T3 and T4 are ON, and one of either T1 or T2 is ON. If T1 is ON, as soon as the row select signal is applied, the voltage level on bit lineCdrops slightly because it is pulled down by T1 and T3. The data read circuitry detects the small voltage difference

VDD VDD VDD VDD Precharge devices Bit line C T5 T3 T1 T2 T6 T4 Bit line C_⬘ Row

select Word line

1-Bit CMOS SRAM cell

CLK WT1 WB Data write circuitry WB⬘ WT2 Column select Cross coupled sense amplifier Current-mirror differential sense amplifier Read select CLK Data out

FIGURE 2.22 CMOS SRAM cell with read amplifier and data write circuitry [6].

between theCandC0lines (C0is higher) and amplifies it as a logic ‘‘0’’ output. If T2 is ON, as soon as the row select signal is applied, the voltage level on complementary bit lineC0drops slightly because it is pulled down by T2 and T4. The data read circuitry detects the small voltage difference betweenCandC0

lines (Cis higher) and amplifies it as logic ‘‘1’’ output. The data read circuitry can be constructed as a simple source-coupled differential amplifier or as a differential current-mirror sense amplifier circuit (as indicated in Fig. 2.22). The current-mirror sense amplifier achieves a faster read time than the simple source-coupled read amplifier. The read access speed can be further improved by two- or three-stage current mirror differential sense amplifiers [6].

2.1.4.2 Dynamic RAM Circuits

All RAMs lose their contents when power supply is turned off. However, some RAMs gradually lose the information even if power is not turned off, because the information is held in a capacitor. Those RAMs need periodic refreshing of information in order to retain the data. They are called dynamic RAMs or DRAMs.

Static RAM cells require 4–6 transistors per cell and need 4–5 lines connecting to each cell including power, ground, bit lines, and word lines. It is desirable to realize memory cells with fewer transistors and less area, in order to construct high density RAM arrays. The early steps in this direction were to create a 4-transistor cell as in Fig. 2.23a by removing the load devices of the 6-transistor SRAM cell. The data is stored in a cross-coupled transistor pair as in the SRAM cells we discussed earlier. But it should be noted that voltage from the storage node is continuously being lost due to parasitic capacitance, and there is no current path from a power supply to the storage node to restore the charge lost due to leakage. Hence, the cell must be refreshed periodically. This 4-transistor cell has some marginal area advantage over the 6-transistor SRAM cell, but not any significant advantage. An improvement over the 4-transistor DRAM cell is the 3-transistor DRAM cell shown in Fig. 2.23b. Instead of using a cross-coupled transistor pair, this cell uses a single transistor as the storage device. The transistor is turned ON or OFF depending on the charge stored on its gate capacitance. Two more transistors are contained in each cell, one used as read access switch and the other used as write access switch. This cell is faster than the 4-transistor DRAM cell; however, every cell needs two control and two I=O (bit) lines making the area advantage insignificant.

The widely popular DRAM cell is the single transistor DRAM cell shown in Fig. 2.23c. It stores data as charge in an explicit capacitor. There is also one transistor which is used as the access switch. This structure consumes significantly less area than a static RAM cell. The cell has one control line (word line) and one data line (bit line). The cells can be selected using the word line, and the charge in the capacitor can be modified using the bit line.

2.1.4.3 Read Only Memories (ROMs)

ROM arrays are simple memory circuits, significantly simpler than the RAMs, which we discussed in the preceding section. A ROM can be viewed as a simple combinational circuit, which produces a specified output value for each input combination. Each input combination corresponds to a unique address or location. Storing binary information at a particular address can be achieved by the presence or absence of a connection from the selected row to the selected column. The presence or absence of the connection can be implemented by a transistor. Figure 2.24 illustrates a 434 memory array. At any time, only one word line among A1, A2, A3, and A4 is selected by the ROM decoder. If an active transistor exists at the cross point of the selected row and a data line (D1, D2, D3, and D4), the data line is pulled low by that

TABLE 2.1 Write Operation Summary of the SRAM Cell Shown in Figure 2.22

Desired Action WB WB0 Operation

WRITE 1 0 1 WT1 OFF, WT2 ON, forcingC0low WRITE 0 1 0 WT1 ON, WT2 OFF, forcingClow

Do not write 0 0 WT1 and WT2 OFF, forcingCandC0to be high

transistor. If no active transistor exists at the cross point, the data line stays high because of the PMOS load device. Thus, absence of an active transistor indicates a ‘‘1’’ whereas the presence of an active transistor indicates a ‘‘0’’.

ROMs are most effectively used in devices, which need a set of fixed values for operation. The set of values are predetermined before fabrication and a transistor is made only at those cross-points where one is desired. If the information that is to be stored in the ROM is not known prior to fabrication, a transistor is made at every cross-point. The resulting chip is a write-once ROM. The ROM is pro- grammed by cutting the connection between the drain of the MOSFET and the column (bit) line. ROMs are effective in applications where large volumes are required.

2.1.5

Low-Power CMOS Circuit Design

The increasing importance and growing popularity of mobile computing and communications systems have made power consumption a critical design parameter in VLSI circuits and systems. The design of

Bit line C Bit line C_⬘

Parasitic storage capacitances Word line Read Parasitic storage capacitances Bit line (write) Write Bit line (read) (a) (c) (b) Bit line (data read/write) Word line (read/write select) Explicit storage capacitances

FIGURE 2.23 Different configurations of a DRAM cell: (a) 4-transistor DRAM cell, (b) 3-transistor DRAM cell, (c) 1-transistor DRAM cell.

portable devices requires consideration of the peak power for reliability and proper circuit operation, but more critical is the time-averaged power consumption to operate the circuits for a given amount of time to perform a certain task [11,12]. There are four sources of power dissipation in digital CMOS VLSI circuits, which are summarized in the following equation:

Pavg¼PswitchingþPshort-circuitþPleakageþPstatic