Effects of Single Event Upset in the Configuration Memory of

An FPGA can contain millions of configuration bits controlling the routing structure and the logic blocks. SEUs in the configuration memory of an SRAM-based FPGA may disrupt the routing architecture of the implemented circuit and the behaviour of the functional units. Such faults may be considered permanent because the configuration memory is usually not written again after the first configuration.

From a modeling point of view, SEUs affecting the configuration memory of an FPGA device may not be modeled by the stuck-at model that is generally assumed for digital circuits. A more accurate fault model has to be considered, as shown in [155] for logic resources and in [186] for routing resources. In the following we present the fault model that has been considered in the design of the presented software tools.

The model of SEUs affecting configuration bits controlling logical resources

The tools presented in this thesis adopt the functional fault model for SEUs affecting the configuration bits controlling the logic resources of FPGAs proposed in [155]. This fault model has been demonstrated to be much more accurate than the stuck-at fault model when the problem of analysing the effects of SEUs in SRAM-based FPGAs is addressed.

In the stuck-at fault model, a SEU in the configuration memory of a component causes the output of the component to be stuck at a given value, thus the faulty com- ponent always produces an incorrect value. In our simulator, a SEU in the configura- tion memory of a LUT causes an alteration of the functionality performed by the LUT. In particular, the faulty LUT will produce an incorrect value only when the configuration

of its input values is the one associated with the faulty configuration bit, while for every other configuration of its input values the faulty LUT will behave correctly. Figure 3.6(a) shows a SEU causing a bit flip in the configuration bit associated with input (0 0 0 0). In this case the logic function implemented by the LUT changes from the correct function y = x1· x2+ x3· x4to the faulty function yf= x1· x2+ x3· x4+ ¯x1· ¯x2· ¯x3· ¯x4.

(a) SEU in a lookup table. (b) SEU in a I/O buffer.

Figure 3.6. Effects of SEUs in the logic components of an FPGA.

It may be observed that in the example the behaviours of y and yf are different only when the values of the input signals are (0000).

A SEU in the configuration bit of an I/O buffer causes an undesired connection or disconnection between two wires, as shown in Figure 3.6(b).

The model of SEUs affecting configuration bits controlling routing resources

To show the model of SEUs [186], let us consider the switch block shown in Fig. 3.7, where two PIPs connect wire A to B and wire C to D, respectively. Depending on the position and the electrical properties of the affected PIP, an SEU in the routing structure can cause the following topological modifications (also shown in Fig. 3.7): • Open, where the PIP is not programmed any more and thus the corresponding

connection (A → B) is deleted.

• Antenna, where a new connection (unused → B) is added between an unused input node and a used output node.

• Conflict, where a new connection (A → D) is added between a used input node and a used output node.

• Bridge, where an existing connection is deleted (C → D) and a new one (A → D) is added between a used input node and the output node of the deleted connec- tion.

• Unrouted, where the modification of the routing structure of the system induced by the SEU in the configuration bit controlling the PIP cannot be classified in any of the previous categories.

3.3. EFFECTS OF RADIATION ON FPGA DEVICES Correct configuration Open Antenna Conflict _Bridge D A B C D A B C D A B C D A B C D A B C

Figure 3.7. Effects of SEUs in the routing components of an FPGA.

Effects of SEUs in PIPs involving unused connections are not considered as they do not cause a faulty behaviour since they do not affect the system.

Figure 3.8 shows the distribution of the effects of SEUs in the configuration bits controlling routing resources [186]. It appears evident that the major effects are open and conflict.

Figure 3.8. Distribution of the effects of SEUs in the configuration bits controlling routing re-

The effects of the modification of the routing structure of the system induced by SEUs in configuration bits controlling PIPs can be mapped on modifications of the behaviour of logic components of the netlist at a higher level of abstraction. The fol- lowing logical effects can be induced by SEUs in configuration bits controlling routing elements [186]:

• Stuck-at: A node is stuck at a constant logic value. • Bridge: Two nodes exchange their values.

• Wired-AND (Wired-OR): The value of a node C is the AND (OR) of the values of two nodes A and B.

• Wired-MIX: The values of two nodes A and B are mixed as follows: If the values A and B are equal, A and B keep their correct values, otherwise A takes the zero logic value and B takes the one logic value.

K

S

Figure 3.9. Routing example.

With reference to Fig. 3.9, if S is a switch box, C and D are two components directly connected to S, Ci and Dj are the input pins of C and D connected to S through the PIPs Pi and Pj, respectively, the five possible effects of a SEU in the configuration bit controlling P are modeled as follows:

• A stuck-at on Piis modeled by setting the logic signal on Ciat the corresponding fixed value.

• A bridge between Piand Pjis modeled by exchanging the logic values on Ciand Dj.

• A Wired-AND (Wired-OR) between Piand Pjis modeled by setting the logic sig- nals on Ciand on Djto the value PiAND (OR) Pj.

• A SEU causing a Wired-MIX between Piand Pj is modeled by setting the logic signals on Ci to 1 and on Dj to 0 if Pi 6= Pj, while leaving Ci and Dj unaltered otherwise

It may be observed that a given SEU in the configuration bit associated with a PIP can propagate to different routing segments, and that the same SEU can have different effects on the routing segments through which it propagates.

3.3. EFFECTS OF RADIATION ON FPGA DEVICES

Table 3.1. Correspondence between physical and logic effects of SEUs in tile routing PIPs.

Physical Modification Logic Effect Conflict Wired-AND Open Stuck-at 0 Bridge Bridge Antenna Stuck-at 0

Table 3.2. Correspondence between physical and logic effects of SEUs in tile routing PIPs.

Physical Modification Logic Effect Conflict Wired-AND Wired-MiX Open Stuck-at 1 Bridge Bridge Antenna Stuck-at 0

Table 3.3. Correspondence between physical and logic effects of SEUs in tile routing PIPs.

Physical Modification Logic Effect Conflict Wired-AND Open Stuck-at 0 Bridge Bridge Antenna Stuck-at 0

In particular the effect of a SEU in the configuration memory controlling a PIP depends on the position of the PIP with reference to the levels of routing introduced in Section 2.1.2. The logical effects corresponding to the physical modifications induced by SEUs in the configuration bits controlling PIPs belonging to the tile routing, local routing and multiple-tile routing are summarized in Table 3.1, Table 3.2 and Table 3.3 respectively [186].

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