An efficient ADC implemented with a pulse frequency mod-

The architecture of a pulse frequency modulator with multibit output was already shown in Fig. 3.25, where we used the PFM interpretation to analytically calculate the spectrum of the output signal yn[N ]. Now, we will retake that architecture

to talk more about it. For the moment, we will ignore the delay line of the figure and we will focus on the pulse frequency modulator block, which is already well-known for us. To match with the performance of a conventional VCO-based ADC, we must satisfy:

Td=

1 fs

= Ts, (4.3)

where fs is the sampling frequency.

If signal p(t) was sampled, the output spectrum would be first-order noise shaped. According to the PFM interpretation, we can define a linear model of the pulse frequency modulator (for simplicity, we do not take into account the DC component fo). This model is shown in the left side of Fig. 4.6, expressed

in terms of the Laplace ‘s’ variable. Based on this model, the pulse frequency modulated output signal (P (s)) can be calculated. To identify a sampled signal in the equations, we use the star operator (·)*, as defined in [32]:

P∗(s) =  KVCO· 1_{− e}−sTs s X(s) + 1_{− e}−sTs s M (s) ∗ . (4.4) Supposing that fx  fs: 1− e−sTs s X(s)≈ X(s), (4.5)

Chapter 4. VCO-based single stage architectures we get: P∗(s) ≈ KVCO· X∗(s) + 1 − z−1
 M (s) s ∗ . (4.6)

Equation (4.6) shows that the system works similar to a first-order ∆Σ modulator, as expected. Whereas the input signal X(s) is seen at the output as it is but multiplied by the VCO gain, the modulation components M (s) are first-order noise shaped. Consequently, the pulse frequency modulator architecture could be used itself as an ADC. Unfortunately, p(t) is a single bit signal, so that, if we consider it as our converter output signal, it will take us to an inefficient structure. We will explain next how this architecture can be transformed into an efficient ADC.

VCO-based ADCs implemented with ring oscillators are typically built with multiphase ring oscillators [41] that produce a multibit output. In the case of PFM-based ADCs, a multibit output can be implemented if the oscillating signal p(t) is sampled after a continuous-time FIR filter [90] using, for example, the delay line configuration of Fig. 3.25(a). In the right side of Fig. 4.6(b) we can see the Laplace model of this delay line. Now, the output of the system is defined as follows: Y_N∗(s) = N X n=1 e−s·nTsN · P (s) !∗ . (4.7)

If we make the same assumptions as before, we get the following expression for YN(s)∗: Y_N∗(s) ≈ N · KVCO· X∗(s) + 1 − z−1
N X i=1 e−s·iTsN M (s) s !∗ . (4.8)

Equation (4.8) shows that the modulation components are filtered by an addi- tional low-pass FIR filter, at the same time that the input signal is multiplied by the term N . Let’s now check whether the addition of the delay line to the system supposes a SNDR improvement. With that purpose in mind, we will study the differences between the equations that describe both the single-phase and the multiphase cases, i.e. (4.6) and (4.8) respectively.

On the one hand, regarding the STF derived from (4.6) and (4.8), we get the following ratio: STFmultiphase STFsingle-phase = N · KVCO KVCO = N. (4.9)

On the other hand, obtaining the same ratio for the NTF (here we suppose that our noise term is M (s)/s) is more difficult because the equations of the NTFs involve expressions that can not be easily simplified. This ratio is defined

4.2. ADC circuits based on an analog pulse frequency modulator

Figure 4.7: Spectral representation of the NTFs of both the single-phase and the multiphase pulse frequency modulator architectures: (a) in the continuous domain, and (b) in the discrete domain (after sampling).

as follows: NTFmultiphase NTFsingle-phase = 1 − e−s·Ts
 PN n=1e −s·nTs N  (1 − e−s·Ts) = N X n=1 e−s·nTsN. (4.10)

As can be observed, the relation is non-intuitive and no meaningful results can be concluded at a glance. However, empirical conclusions can be obtained from numerical estimations. Firstly, we have calculated the representation of both NTFs for a limited spectral gap. If we suppose, for instance, Ts = 1 s and N =

15, the spectral representation looks as in Fig. 4.7(a). The shape of the NTFs is composed of a set of lobes with nulls in the multiples of fs. When sampling, these

lobes alias and generate the shapes shown in Fig. 4.7(b). It can be appreciated that both NTFs overlap and the difference between their values is negligible. From these numerical results, we can empirically establish that the ratio between the NTFs is equal to one. Although it is an empirical observation, it fits very well with the results obtained later on by simulation.

According to (4.9) and the results depicted in Fig. 4.7(b), we are able to deduce the following relationship between the SNDR for the single-phase case

Chapter 4. VCO-based single stage architectures

Figure 4.8: Behavioral simulations of both the single-phase and the multiphase pulse frequency modulator architectures (the output spectrum is normalized with respect to the output of the single-phase case).

and the SNDR for the multiphase case:

SNDRmultiphase = SNDRsingle+ 20 log10(N ). (4.11)

To validate (4.11) we have used a behavioral model of the system shown in Fig. 4.6, both considering p(t) and yN(t) as the outputs of the system. Just to

provide an example, Fig. 4.8 depicts the output spectra of both cases with a -3 dBFS sinusoidal input wave, OSR= 128, fo = KVCO = fs/32, and N = 15.

Firstly, we can observe that the power level is similar in both cases according to the results of Fig. 4.7(b). Secondly, the difference between the SNDRs is equal to 23 dB. According to (4.11), we expect a difference approximately equal to 23.52 dB, therefore our prediction matches with the simulated results.

Then, the delay line of the Fig. 4.6(a) allows us to build a multibit pulse frequency modulator with improved SNDR. Now, we will propose a circuit to implement this multibit architecture.