EFG Hardware Design

The Error Frame Generator (EFG) prototype was wire-wrapped and implemented on a Euro-card. Wire-wrapping technique is used to allow more densely integrated circuit design and orientation. The following issues were highlighted during the course of EFG hardware design and development.

6.4.1 Clock Synchronisation

When the start of frame (SOF) of CAN frame is detected, all CAN controllers will synchronise their local clock at the same instant. Using the local crystal oscillator, each controller can then measure the exact bit period, tbit for the correct sampling instant. Similarly, the EFG pattern recognition hardware must be able to synchronise itself to the SOF and maintain the correct bit period, tb« until the end-of-frame. This precise timing for EFG unit is provided by the EXO-3 crystal oscillator with an 8-bit counter as the clock prescaler.

6.4.2 Hardware based CAN Message Screeners

From Section 6.3 of the EFG hardware design, it can be seen that a pattern recognition hardware is used to screen for the required CAN identifier, rather than the conventional way o f using CAN controller. CAN controller is not used for detecting the CAN identifier in this instance due to the following reasons.

The CAN controller only flags an interrupt when a complete CAN frame has been received, i.e. an acknowledgement has been given by the receiving node. This could not be used for the purpose of error injection. The active error flag must he incident upon the transmitting CAN frame in order to forge

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Chapter 6 - The Error Frame Generator Design

the error condition. If the active error frame is not precisely incident on the CAN message frame (which is to be zapped into bus-off state), other nodes on the network will be affected by the EFG unit.

Legend

Ack : acknowledgement S : stuff bits

CRC : cyclic redundancy check SOF : start of frame EOF : end of frame tbit : bit period, c.g. 8ps for RTR : remote transmission request 125kbil/s bus

Figure 6-6 A CAN message frame with reference to the bit period clock, tbu

Figure 6-6 shows a typical CAN message frame. The shaded area indicates the area of interests to the pattern recognition unit, i.e. the hardware based CAN message screener. The area consists o f the arbitration field (the 11-bit identifier and 1 bit RTR), 2 reserved bits and the most significant bit of the control field o f the CAN frame.

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Chapter 6 - The Error Frame Generator Design

Start of Frame Acknowledgement

Delimiter 11 Arbitration Field | j j | | End of

■ j.' Frame

t a r b

^

---t r s p

Figure 6-7 The definition of EFG response time

From Figure 6-7, the following relationships can be established, i.e.

trs p = fm sg " t arb

where

trsp := the time taken for EFG unit to recognise the required CAN identifier and transmit an active error frame

tmsg := the CAN message frame validity period tarb := the arbitration field validity period

For successful error injection, the error frame generation unit must fulfil the following criterion,

i.e.:-trs p ^ tm s g “ ta rb

In other words, the transmission o f the active error frame must be carried out before the temporal validity o f the message frame has ended. The transmission of active error frame on the transmitting message forces the transmitter node to believe that it has caused an error. The transmitter will then initiate the error recovery sequences at once.

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Chapter 6 - The Error Frame Generator Design

The shortest CAN frame consists of 47 bits (assuming zero length message with no stuff bits). First, the EFG unit must determine the CAN identifier by scanning the arbitration field. Once the correct CAN identifier is obtained, the EFG logic must be armed to transmit an active error frame, all within the 35 bit (i.e. 4 7 - 1 2 bit arbitration field) time. The designed EFG unit has successfully fulfilled these criteria.

6.4.3 EFG Response Time

The tbit will be different for different DeviceNet baud rate. For example, if the DeviceNet network is operating at 125 kbit/s.

Period, t = ---1 frequency, /

1 tbil " 125A:

= 8 ps

Table 6-8 The relationships between baud rate and the bit period, tbii

Baud Rate 125 kbit/s 250 kbit/s 500 kbit/s

Bit Period, tbit 8 ps 4 ps 2 ps

At the fastest baud rate, i.e. 500 kbit/s, the turn-around response time, trsp of the EFG unit must be less than 2ps x 36 bits = 72 ps (the period from control field to the acknowledge field, assuming no stuff bits involved). If the EFG logic fails to deliver an active error flag within this response time, then the EFG unit will not be successful in injecting error on the target node.

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Chapter 6 - The Error Frame Generator Design

The EFG unit designed in this project has successfully satisfied this crucial criteria. It has demonstrated its capability to zapp off the zero length CAN message frame successfully at 125kbit/s.

6.4.4 CTE Baud Rate Setting

In the EFG unit, the global clock is provided by the EXO-3 programmable crystal oscillator. The current design uses 3 DIP switches to manually set the EFG unit into one of the three different baud rates of DeviceNet. Even though it is possible to program the oscillator using the Philips 592 microcontroller, it is not adopted in the current design. The choice between manual and software controlled baud rate settings is only a matter of individual preference.