Electrical characterization 57

The entry level electrical characterization of the heterostructures is accomplished via Hall measurements-Van der Paw configuration at room temperature. Hall measurements results are decisive for further sample processing. This technique provides the carrier nature (holes – electrons) and its density (including parallel conduction if any). It should be pointed out that HFETs based on GaN/AlGaN or GaN/InAlN heterostructures such as the ones shown in Figure 5.1 exhibit always n-channels. In all studied cases mobility was around 1x103 _cm2 _V- 1_S-1 _{or higher and 2DEG density higher than 1.2 x10}13 _cm-2_{. Samples with lower carrier}

mobility and/or carrier density are discharged from the study.

5.6.2 Devices

Direct current voltage-current characteristics either both input, gate-source voltage (VGS)-

gate current (IGS) and output, drain-source voltage (VDS) - drain current (ID), as well as

transconductance (Gm) were measured and used to evaluate the DC performance of the devices. Devices with IGS <100 µ mm-1, Gm >100 mS mm-1, and ID > 350 mA mm-1 were

selected. High ID ismandatory for high power applications. Gm is capital for power amplifier

gain. While a low IGS (leakage current) level is important to reduce IGS side effects (i.e. drain

current lag and poor device reliability), it is also relevant for a meaningful low noise frequency characterization of the device.

Capacitance-voltage (C-V) measurements were accomplished with a RLC meter. From the C-V measurements, apparent carrier concentration profile, n (cm-3) normal to the growth direction versus depth (nm), were calculated by using the equations:

n 2 ₁

depth

n vs depth curves were used to judge the widening of the carrier concentration. Standard heterostructure exhibits, usually, a narrow peak. While multiple channel HFETs, usually, present one or two peaks. And in general the carrier concentration profile is wider than that for a standard structure. Knowledge of the carrier density profile is important in terms of evaluation of the effectiveness of the heterostructure on widening the 3DEG density profile. It worth to mention that results from C-V profile should be taken “qualitatively” since this method has several limitation. Among which Debye length is the most important in the definition of the carrier density profile (see APPENDIX A ).

Measurement of s-parameters is carried out with a vector network analyzer in the range of frequencies 2-20GHz. Cut-off frequency, fT, defined as extrapolation of

2 21

h to zero dB. And

21

h short circuit current again, is calculated from s-parameters as

/ | .

Gate-source voltage (VGS) and drain-source voltage (VDS) at which fT is achieved are recorded

for further analysis. Studied devices exhibit a fT in the range 10-14 GHz. This technique is

crucial to evaluate the bias point at which plasmon-hot phonon resonance in gated HFETs is attained. Since no other technique is applicable. s-parameters together with a HFET small- signal equivalent electrical circuit Figure 5.13 help to find out extrinsic and intrinsic parameters by extraction techniques. Then it is possible to reconstruct the intrinsic equivalent

circuit. Of principal interest are gate-source capacitance (Cgs), and gate drain capacitance

(Cgd). Which are related with the intrinsic cut-off frequency in the following manner

,

2

2

where is the small signal transconductance, the saturation velocity, and the gate width.

Extrinsic parameters are useful in finding out a better approximation to the real conditions, electric field in the channel, at which cut-off frequency occurs. That is to say, bias conditions at which phonon effects are minimized. From the measurements of the fT, intrinsic transient

time, τint, is calculated. Under high electric field but lower than critical electric field (Ecri),

shorter τint implies higher saturation carrier velocity, , therefore, shorter hot-phonon

lifetime. τint, is calculated as follow, the total transient time is τTotal= τint + τD + τRC = (2π f T )-1

, where τD is the drain time constant and τRC is the charging delay time constant. From the

τTotal versus channel voltage, Vch = VDS – ID (RS – RD), and τTotal versus 1/ ID characteristics

we obtained τint + τRC and τint + τD, extrapolating τTotal , respectively, for Vch and1/ ID tending

to zero.

In order to evaluate the reliability of the devices, a series of stress at four different bias points were carried out. The bias points are: (1) on-state-low-field stress (VGS = 0 V,

VDS = 7 V), (2) reverse-gate-bias stress (VGS = −20 V, VDS = 0 V), (3) off-state-high-field

stress (VGS = −10 V, VDS = 20 V), and (4) on-state-high-field stress (VGS = 0 V, VDS = 20 V).

Mentioned electrical stress tests are realized, also, at high temperature, up to 200°C.

Low frequency noise (LFN) characterization of the devices before and after stress them is accomplished with the help of a phase noise measurement system. See Figure 5.14. Characteristic noise signal from HFET are built up, usually, by a superposition of 1/f –like noise, generation-recombination (G-R) noise, and white noise. The latter, frequency independent is related with the device temperature and impose a minimum detectable noise level. In practice this level is set by either both the device under test (DUT) or the set up used to measure the noise. In this case our Test set has a noise level well below -180 dB V/Hz, which corresponds to a power density of -167dBm/Hz at an input impedance of 50 Ω. The thermal noise power density is -174dBm/Hz, which is about 7dB lower compared to the noise floor of the Test set.

G-R noise in semiconductors is related with the generation and recombination of carries. G-R results in a fluctuation in the number of carriers contributing to the current transport. G-R power spectrum density (PSD), Lorentzian in nature, is given by the McWhorter’s number fluctuation as follow:

4Δ

1 2

When a large number of trap (number fluctuation) are presented, G-R noise exhibit 1/f –like noise provided trap time constant are distributed as follow:

1

ln , 0 otherwise.

Because G-R noise is relevant within a few kT from the Fermi energy level and owing to the pining of Fermi energy level in nitrides, G-R noise in nitrides is mostly due to the deep traps. Traps closer to the conduction or valence band will stay most of the time either empty or filled. PSD general expression for 1/f –like noise is proportional to 1 f , with

0.3 

1.3

 is found from the phenomenological relation between 1/f and the inverse of the total number of charge carriers, N, in the channel in homogeneous samples. This relation is called Hooge and is given by:

where ( )S f is the current spectral density, _I _H is the dimensionless Hooge’s parameter, N is the number of electrons scattered by A lattice nodes.

Figure 5.14 Block diagram shows the Agilent E5505A residual phase-noise measurement setup with the single-sided spur calibration technique. Calibration source and 10 dB attenuator attenuator are only used for calibration purpose. DUT stands for device under test.

Fluctuation in current may be caused by either both mobility fluctuation and number carrier fluctuation. Carrier fluctuation can be described by McWhorter’s number fluctuation, while mobility fluctuation can be described by Hooge phenomenological formulation. Both fluctuations may exhibit 1/f –like PSD. Therefore, sometimes it is not possible to discerner between carrier or mobility fluctuations. And extra measurements (e.g. pulse measurements, high temperature measurements) and or stress the device are necessary in order to elucidate the nature of noise. Difference in LFN levels is an indication of the degradation of the device after being stressed. It is expected, for example, that when the stress takes place under plasmon-hot phonon resonance conditions, the device be minimally degraded because the effect of hot phonon is minimized. In order to corroborate result from the stress/measurements usually an ensemble of the devices on the same sample is studied, and a representative value is taken for every single measured variable.