Bus Encoder/Decoder Implementation

There is a practical issue using bus encoding algorithms such as DBM/VBM and bus invert with commodity memory devices that do not have built in bus encoding/decoding hardware [127]. Nearly all bus encoding algorithms rely on knowledge of the previous bus value to determine the current bus value. The codeword value is dependent on the context in which it was encoded. It is difficult to use such algorithms with commodity memory devices because, to obtain the expected transition reduction, the data must be read in the same context it was saved. For the DBM/VBM algorithm, the data cannot even be correctly decoded if it is read in a different context to which it was written.

The issue of context is a problem for the video compression specific bus encod-ing proposal given in [128]. This uses DBM/VBM, but to exploit the correlation between multiple reference frames, encodes/decodes one reference frame in the context of another. If used with a commodity memory device, encoding reference frames in this way makes it impossible to access them on an individual basis.

Thus it would be impossible to use the proposal given in [128] with commodity memory devices. In general, the context issue is mitigated in video compression systems because the video data is typically saved and loaded in macroblock sized chunks. Each word written to memory is loaded in the same context in which it was saved.

Nearly all bus encoding studies have been focused on ASICs. Implementing bus encoding techniques on FPGAs is challenging due to the high power cost associated with FPGA logic. The power used to implement the bus encoding and decoding operations can frequently outweigh the power saved by reducing the transitions on the bus. Only the authors of [129] have studied bus encoding

Figure 6.5: DBM/VBM Encoding Process

specifically on FPGAs. The results given in [129] indicate that for their chosen FPGA (A Virtex Device) their algorithm and architecture would not result in an overall power saving for realistic bus capacitance values. In this section, the implementation of DBM/VBM encoder architecture is pursued because as shown in section 6.3.1, this algorithm in combination with the proposed adaptive propagation algorithm provides the greatest reduction in transitions.

6.2.1 DBM/VBM Algorithm Overview

The DBM/VBM algorithm is specifically designed to reduce transitions on corre-lated input data [126]. A diagram of the DBM/VBM encoding process is shown in Figure 6.5. Difference Based Mapping is the first stage of the encoding pro-cess. The purpose of this stage is to remove the redundancy, present in the input data. The DBM algorithm does this by computing the difference between the previous input value and the current input value. The difference is then mapped to a positive value within the range 0 to 2^N − 1, where N is the bit width of the input data.

The second stage, Value Based Mapping, can be viewed as an entropy en-coding process. The aim being to reduce the number of transitions on the VBM

Input Output

Table 6.1: VBM codetable for a bit width of 3

output instead of reducing the output bitrate, as would be the aim in conven-tional entropy encoding. The XOR gate and register convert any logic 1 produced by the entropy encoder into a transitions on the output bus. To minimize the number of transitions the entropy encoder matches the number of bits in the output word with logical value of 1 to the probability of an input word occurring.

The greater the probability of an input word occurring, the fewer the number of logic 1 bits in the output word. VBM assumes that the probability of an input word occurring decreases as the value of that word increases. Thus, for VBM the number of ones in the output word increases as the value of the input word increases. The VBM code table for a bit width of 3 is shown in table 6.1. The DBM/VBM decoding process is simply the inverse of the encoding process. More details on the DBM/VBM encoding algorithm are given in [126]

6.2.2 DBM/VBM Implementation

As previously stated a memory bus width of 32 bits has been assumed. This does not require a DBM/VBM encoder and decoder which supports 32-bit oper-ation. The hardware required would be too complex. More importantly it would offer little benefit because the video data will only be correlated, and hence the

Figure 6.6: Simplified diagram of a DBM encoder

DBM/VBM coding scheme effective in reducing transitions, if it is considered in segments which have a bit width which is less than or equal to the pixel bit width (8 bits).

DBM is primarily an arithmetic operation. As such it can be efficiently im-plemented using the optimised carry chain logic present in the Cyclone-3 FPGA used. A diagram of the implementation is shown in Figure 6.6. Not shown on the diagram are the control inputs to the 4 to 1 multiplexer. Sel(0) is one if In(t) ≥ In(t − 1) else it is zero. Sel(1) is one if |In(t) − In(t − 1)| >

(In(t − 1) ⊕ M SB(In(t − 1)) else 0. The DBM decoder is implemented in a similar way.

An algorithm for implementing the VBM operation is given in [126]. Im-plementing this algorithm would require either multiple clock cycles per result (up to the number of bits in the VBM input/output), or a significant block of combinatorial logic without any registers. Both options are undesirable as they would have a large impact on an overall system, either by reducing the available memory bandwidth, or, by reducing the clock rate the system can operate at.

Therefore, only direct combinatorial implementations have been considered.

Figure 6.7: Different DBM/VBM Encoding Structures Implemented, 8-bit DBM/8-Bit VBM and 8-bit DBM/4-bit VBM. The decoding structures are sim-ilar.

The critical parameter in a direct combinatorial implementation is the bit width of the VBM encoder used. As already mention the maximum useful width is 8 bits. Directly implementing an 8-bit VBM encoder requires significant logic resources, as it requires the eight 8-bit functions to be implemented. A 4 bit VBM encoder can be implemented much more efficiently as each output bit can be produced using only 1 LUT. However, reducing the width of the VBM encoder increases the transitions on the output bus. However, since the overall aim of the encoding process is to reduce the total power used this may not be a great disadvantage given the much higher resource, and hence power cost, of 8-bit VBM encoding. Two DBM/VBM encoding/decoding structures were therefore implemented. One using 8-bit DBM and VBM encoders, the other using 8-bit DBM encoders and 4-bit VBM encoders. A diagram of each structure is shown in Figure 6.7.