4.17 AC Specifications
4.17.3 Ethernet timing
The Ethernet provides both MII and RMII interfaces. The MII and RMII signals can be configured for either CMOS or TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V. Please check the device pinout details to review the packages supporting MII and RMII.
First Data Last Data
SCK Input
4.17.3.1 MII receive signal timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)
The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%.
There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the RX_CLK frequency.
Note: In the following table, all timing specifications are referenced from RX_CLK = 1.4 V to the valid input levels, 0.8 V and 2.0 V.
Figure 33. MII receive signal timing diagram
4.17.3.2 MII transmit signal timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)
The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%.
There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the TX_CLK frequency.
The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from either the rising or falling edge of TX_CLK, and the timing is the same in either case. This option allows the use of non-compliant MII PHYs.
Refer to the SPC584Gx, SPC58EGx, SPC58NGx 32-bit Power Architecture microcontroller reference manual’s Ethernet chapter for details of this option and how to enable it.
Note: In the following table, all timing specifications are referenced from TX_CLK = 1.4 V to the valid output levels, 0.8 V and 2.0 V.
Table 50. MII receive signal timing
Symbol C Characteristic
Value
Unit
Min Max
M1 CC D RXD[3:0], RX_DV, RX_ER to RX_CLK setup 5 — ns
M2 CC D RX_CLK to RXD[3:0], RX_DV, RX_ER hold 5 — ns
M3 CC D RX_CLK pulse width high 35% 65% RX_CLK period
M4 CC D RX_CLK pulse width low 35% 65% RX_CLK period
M1 M2
RX_CLK (input)
RXD[3:0] (inputs) RX_DV RX_ER
M3
M4
Figure 34. MII transmit signal timing diagram
4.17.3.3 MII async inputs signal timing (CRS and COL)
Figure 35. MII async inputs timing diagram Table 51. MII transmit signal timing
Symbol C Characteristic
Value(1)
Unit
Min Max
M5 CC D TX_CLK to TXD[3:0], TX_EN, TX_ER invalid 5 — ns
M6 CC D TX_CLK to TXD[3:0], TX_EN, TX_ER valid — 25 ns
M7 CC D TX_CLK pulse width high 35% 65% TX_CLK period
M8 CC D TX_CLK pulse width low 35% 65% TX_CLK period
1. Output parameters are valid for CL= 25 pF, where CL is the external load to the device. The internal package capacitance is accounted for, and does not need to be subtracted from the 25 pF value
M6 TX_CLK (input)
TXD[3:0] (outputs) TX_EN TX_ER
M5 M7
M8
Table 52. MII async inputs signal timing
Symbol C Characteristic
Value
Unit
Min Max
M9 CC D CRS, COL minimum pulse width 1.5 — TX_CLK period
CRS, COL
M9
4.17.3.4 MII and RMII serial management channel timing (MDIO and MDC)
The Ethernet functions correctly with a maximum MDC frequency of 2.5 MHz.Figure 36. MII serial management channel timing diagram
4.17.3.5 MII and RMII serial management channel timing (MDIO and MDC)
The Ethernet functions correctly with a maximum MDC frequency of 2.5 MHz.Note: In the following table, all timing specifications are referenced from MDC = 1.4 V (TTL levels) to the valid input and output levels, 0.8 V and 2.0 V (TTL levels). For 5 V operation, timing is referenced from MDC = 50% to 2.2 V/3.5 V input and output levels.
M11 MDC (output)
MDIO (output)
M12 M13
MDIO (input)
M10
M14 M15
Table 53. MII serial management channel timing
Symbol C Characteristic
Value
Unit
Min Max
M10 CC D MDC falling edge to MDIO output invalid
(minimum propagation delay) 0 — ns
M11 CC D MDC falling edge to MDIO output valid (max
prop delay) — 25 ns
M12 CC D MDIO (input) to MDC rising edge setup 10 — ns
M13 CC D MDIO (input) to MDC rising edge hold 0 — ns
M14 CC D MDC pulse width high 40% 60% MDC period
M15 CC D MDC pulse width low 40% 60% MDC period
Note: In the following table, all timing specifications are referenced from MDC = 1.4 V (TTL levels) to the valid input and output levels, 0.8 V and 2.0 V (TTL levels). For 5 V operation, timing is referenced from MDC = 50% to 2.2 V/3.5 V input and output levels.
Figure 37. MII serial management channel timing diagram
4.17.3.6 RMII receive signal timing (RXD[1:0], CRS_DV)
The receiver functions correctly up to a REF_CLK maximum frequency of 50 MHz +1%.
There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the RX_CLK frequency, which is half that of the REF_CLK
frequency.
Table 54. RMII serial management channel timing
Symbol C Characteristic
Value
Unit
Min Max
M10 CC D MDC falling edge to MDIO output invalid
(minimum propagation delay) 0 — ns
M11 CC D MDC falling edge to MDIO output valid (max
prop delay) — 25 ns
M12 CC D MDIO (input) to MDC rising edge setup 10 — ns
M13 CC D MDIO (input) to MDC rising edge hold 0 — ns
M14 CC D MDC pulse width high 40% 60% MDC period
M15 CC D MDC pulse width low 40% 60% MDC period
M11 MDC (output)
MDIO (output)
M12 M13
MDIO (input)
M10
M14 M15
Note: In the following table, all timing specifications are referenced from REF_CLK = 1.4 V to the valid input levels, 0.8 V and 2.0 V.
Figure 38. RMII receive signal timing diagram
4.17.3.7 RMII transmit signal timing (TXD[1:0], TX_EN)
The transmitter functions correctly up to a REF_CLK maximum frequency of 50 MHz + 1%.
There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the TX_CLK frequency, which is half that of the REF_CLK
frequency.
The transmit outputs (TXD[1:0], TX_EN) can be programmed to transition from either the rising or falling edge of REF_CLK, and the timing is the same in either case. This option allows the use of non-compliant RMII PHYs.
Note: In the following table, all timing specifications are referenced from REF_CLK = 1.4 V to the valid output levels, 0.8 V and 2.0 V.
RMII transmit signal valid timing specified is considering the rise/fall time of the ref_clk on the pad as 1ns.
Table 55. RMII receive signal timing
Symbol C Characteristic
Value
Unit
Min Max
R1 CC D RXD[1:0], CRS_DV to REF_CLK setup 4 — ns
R2 CC D REF_CLK to RXD[1:0], CRS_DV hold 2 — ns
R3 CC D REF_CLK pulse width high 35% 65% REF_CLK period
R4 CC D REF_CLK pulse width low 35% 65% REF_CLK period
R1 R2
REF_CLK (input)
RXD[1:0] (inputs) CRS_DV
R3
R4
Figure 39. RMII transmit signal timing diagram