Examples

element to take an input, a clock and an output, and leave out the complementary output and the resets. Since the values that appear at the input, output and the clock are bit values, we use the type of Boolean to denote this. Thus each delay element has the following type:

bool→bool→bool

Delay elements that we have used in our experiments are the rising-edge latch (RE), and an active-high (AH) latch. The rising-edge latch samples the input value at the output at every rising edge of the clock, whereas the active-high latch also known as the level-triggered latch samples the input during the period that the clock is high.

RE (clk :bool) =4 λinp:bool. inp AH (clk :bool) =4 λinp:bool. inp

The definition shown above simply returns the input value at the output, in the same way as a buffer does. However, the exact interpretation, about when these values appear is left for a later stage, and will depend on the context. If we wish to simulate the circuits containing delay elements, in HOL, then we can use an interpreter function written using functions in ML and HOL, that models the actual behaviour of the device. We shall explain about this in detail in a later section. If we want to simulate the circuits containing delay elements in Forte, then they have to be compiled to a flat FSM, and the interpretation of the delay elements takes place in that process. We shall explain more about this in Chapter 7.

This idea of using different interpretations, is similar to the notion of alternative base functions [80] and the non-standard interpretations based circuit analysis [102].

We have shown two different delay elements, so that when we compile the circuits in FSM∗ to FSMs in Forte, we can interpret these delay elements then, and illustrate the behavioural differences. We have modelled simple circuits such as a unit-delay multiplexer, and a comparator using a RE latch while we used the AH latch, to model SRAM and CAMs later in Chapter 9. If one desires to extend the library of delay elements, it can be done by adding more definitions, and suitably interpreting them in the two separate compilation phases later on.

6.6

Examples

In this section we will show examples of modelling circuits using the definitions of functions shown in Level 0 and Level 1.

Modelling basic circuits

Our first example shows how to model basic gates. The definitions of some simple gates are shown in Definition 6.19. The definition relies on using functional blocks, which are presented in Definition 6.18. The functional blocks use the definition of Boolean and, or and not, already defined in HOL.

6.6. Examples 83 Definition 6.18. Functional blocks

inv =4 map (∼) and =4 fold (∧)id or =4 fold (∨)id nand =4 inv ◦ and Definition 6.19. Basic gates

Inv =4 map inv And =4 map and Or =4 map or N and =4 map nand

Our next example is the one showing Boolean bitwise operations. Definition 6.20. Bitwise operations

bAnd =4 Bitwise (∧)Id bOr =4 Bitwise (∨)Id

Now we present the definition of an n-bit comparator. There is nothing in the defi- nition which restricts the size of the comparator. Figure 6.5 shows a 2-bit comparator with a unit-delay.

Comparator

a

b

a

b

i

i

out

ck

o

Figure 6.5: A unit-delay, 2-bit comparator.

6.6. Examples 84 Definition 6.21. Unit-delay comparator

xnor a b = (a ∧ b) ∨ (∼a∧ ∼b)

Comp ck = let comp = Bitwise xnor Id in

map(map(RE (hd(hd ck)))) ◦ And ◦ comp

When we get to evaluate the definition of the comparator, we can specify the buses as a list of Boolean lists. When we say evaluate here, we mean evaluating the function comparator to produce a flat term in HOL, with no structure any more, just a term with each node connected to another by Boolean connectors like ∧, ∨, ∼ and so on. Below we show a HOL session, where we specify the size of the comparator by specifying the two input buses (a and b, of size 2) and the clock. Note that clock (ck) is a non- symmetric input, and the buses [a0;a1] and [b0;b1] are symmetric inputs, clubbed together in a list. A HOL conversion comp conv built from the combinator definitions and a list simplifier (SIMP CONV list ss), is used to evaluate the comparator definition. The output of the conversion is a theorem in HOL, the right-hand side of which is the intended structural flat definition of the comparator. Notice that the semantics of the delay elements have not been interpreted at all, they appear as a primitive in the output. In the next section, we shall provide one way to interpret the delay elements, in a manner that the exact behaviour of the circuit can be simulated at the HOL prompt.

Evaluating the structure

val comp_model_list =

[comparator_def, And_def, and_def, fold_def, xnor_def, toTime_def,

map, Mem, Null_def, Id_def, o_DEF, Foldr, ||_def, id_def, Fork_def, el, Select_def, toTime_def, Tail_def, Bitwise_def, append, hd, tl];

val comp_conv = SIMP_CONV list_ss (comp_model_list);

``comparator [[ck]] [[a0; a1];[b0; b1]]``;

comp_conv it;

> val it =``comparator [[ck]] [[a0; a1]; [b0; b1]]``: term

- > val it =

|- comparator [[ck]] [[a0; a1]; [b0; b1]] =

[[RE ck ((b1 ∧ a1 ∨ ∼b1 ∧ ∼a1) ∧(b0 ∧ a0 ∨ ∼b0 ∧ ∼a0))]] : thm

Mux

The last example in this section is a unit-delay 2-to-1 multiplexer. Again a particular size is not specified in the definition; it is left until we are ready to evaluate the particular instance later. This example shows how more than one non-symmetric input is clubbed together in a single list of non-symmetric inputs. The definition is self explanatory. Figure 6.6 shows an n-bit multiplexer.

6.6. Examples 85 Definition 6.22. Unit-delay multiplexer

ctrl and inp = map (∧(hd inp)) not ctrl and inp = map (∧(∼(hd inp)))

M1inp = (map(ctrl and inp)) ◦ Select 0Id M2inp = (map(not ctrl and inp)) ◦ Select 1Id Auxmux inp = ((M1inp)||(M2inp))

M ux[ck;ctrl] = map(map(RE(hd ck))) ◦ Bitwise (∨) (Auxmux ctrl) Notice, that the effect of mapping the delay elementRE onto the output of the mux circuitry, is to map an instance ofREonto each element of the output bus. This becomes visible in the HOL snippet of the Mux example shown next.

a

out b

ctrl

RE

Figure 6.6: A unit-delay, 2-to-1 multiplexer.