Existing Address Mapping Techniques

There are existing address mapping techniques from previous studies [69, 58, 66, 21, 77, 72]. Industrial address mapping solutions can also be found in motherboard chipsets [27, 70]. This section briefly introduces some of them.

2.6.1.1 Page Interleaving Address Mapping

Page interleaving, also known as page mode interleaving, is one commonly used address map- ping technique [69, 66]. Early SDRAM devices were slow, so it was necessary to interleave data across several SDRAM banks to obtain adequate bandwidth for the processor [14]. As shown in Figure 2.9, the bank index is mapped from the middle order address bits, while channel and rank index are still mapped from the higher order address bits.

Ch Rank Row Bank Column Byte

Figure 2.9: Page interleaving address mapping

With page interleaving, memory blocks adjacent in the physical address space are mapped into the first rows of internal banks within a rank, then the second rows of the banks within the same rank; once all banks of a rank are filled up, allocation continues to the next rank. By this way, memory blocks are actually stridden across different banks intra ranks. For example, memory blocks are allocated in the order of row0/bank0/rank0, row0/bank1/rank0, row0/bank2/rank0, ..., row1/bank0/rank0, row1/bank1/rank0, so on and so forth.

2.6.1.2 Rank Interleaving Address Mapping

Rank interleaving is similar to page interleaving except that memory blocks are stridden across banks not only intra ranks but also inter ranks [58]. Figure 2.10 illustrates rank interleaving address mapping. The rank index is mapped from address bits right above bank index. Rank interleaving increases the possibility of pipelining accesses to different banks crossing different ranks. One disadvantage of rank interleaving is that it may increase the number rank-to-rank turnaround cycles required by DDR2 devices [30].

Ch Row Rank Bank Column Byte

Figure 2.10: Rank interleaving address mapping

2.6.1.3 Address Mapping for Direct Rambus DRAM

Wei-fen Lin et al. pointed out that address mappings affect performance significantly and proposed an address mapping scheme for Direct Rambus DRAM (DRDRAM) [21].

DRDRAM provides a 1.6GB/s bandwidth on a single 16-bit device running at 400MHz clock frequency with double data rate. Each DRDRAM device has multiple banks, allowing pipelining and interleaving of accesses to different banks. DRDRAM device’s split control buses (a 3-bit row bus and a 5-bit column bus) allows the memory controller to send commands to independent banks concurrently [13].

Similar to JEDEC SDRAM, DRDRAM memory space has coordinates of channel, device (equivalent to rank in JEDEC SDRAM), bank, row and column. Channel index is mapped from lower order bits to create a single wider logical channel from several physical channels. Then column, bank and device index are mapped from the next lowest order bits to higher order bits, allocating memory blocks contiguously into rows, then stripping across devices and banks. The highest bits are used as row index. This address mapping is further improved by XORing the device and bank index with the lower bits of row index, as well

2.6 SDRAM Address Mapping 25

Ch

Bank Column offset

XOR

Cache tag

Dev Row

Ch

Bank Dev Column offset

Row

Figure 2.11: Direct Rambus DRAM address mapping

as changing the bit order of bank index to create a more randomized bank interleaving.

2.6.1.4 Permutation-based Page Interleaving Address Mapping

As an improvement to page interleaving address mapping, Zhao Zhang et al. proposed the permutation-based page interleaving address mapping for JEDEC SDRAM [77]. As shown in Figure 2.12, the permutation-based page interleaving XORs bank index with a range of row index bits which correspond to the lowest bits of the L2 cache tag in a cache address. This permutation-based address mapping attempts to convert row conflicts mainly due to L2 conflict misses into accesses to different banks, therefore reduce row conflict rate and preserve the spatial locality in SDRAM rows.

Ch Row Bank Column Byte

XOR

Bank

Row Column Byte

Cache tag

Ch Rank

Rank

2.6.1.5 Intel 925X Chipset Address Mapping

Intel’s 925X chipset uses an SDRAM address mapping method similar to page interleaving. Figure 2.13 shows one address mapping of 925X chipset as the width of row and column index may vary with different SDRAM devices. In addition to mapping bank index from the middle order address bits, a subset of bank and row index bits are reordered [27]. Intel’s 925X chipset supports two dual channel modes, dual asymmetric mode and dual symmetric mode. With dual asymmetric mode, channel index is mapped from the highest address bit, leaving two independent channels. In dual symmetric mode, bit{6} is used as the channel index. Given a 128B cache line size, each cache line strides on two channels. Two 64-bit channels are equivalent to a single 128-bit channel in dual symmetric mode.

Bank

Row Column Byte

Ch

Bank

Row Col Byte

Rank Ch Col

(a) Single channel/Dual asymmetric mode

(b) Dual channel symmetric mode Rank

3-bit

6-bit

Figure 2.13: Intel 925X chipset address mapping

2.6.1.6 VIA KT880 North Bridge Address Mapping

Figure 2.14 shows the address mapping method used in VIA’s KT880 north bridge [70]. The bank index is permanently mapped from address bit{14:13}. As the width of column and row index may vary with different SDRAM devices, row index may be mapped from two segments of address bits right above or below bank index. KT880 also supports dual memory channel. In dual channel mode, the channel index is mapped from address bit{3}. Therefore, each 16-byte memory block strides on two 64-bit channels, also resulting in a 128-bit logical channel.

2.6 SDRAM Address Mapping 27

Row Column Byte

Bank

Row Column Byte

Rank Ch

(a) Single channel mode

(b) Dual channel mode

Rank Bank Row

12-bit

3-bit

Figure 2.14: VIA KT880 north bridge address mapping