3.2.1. Existing Methodologies
It is a common practice that a uniform temperature rise Δ𝑇 due to Joule heating obtained from thermal analysis is simply added to temperature T in expressions used for EM analysis (e.g. Blech based model) without considering the true mutual correlation of thermal and electro-mechanical effects [44, 45, 50]. Undesired chip behaviors as well as time-consuming and non-converging reliability assessments are the common expensive outcomes of such models. It is not surprising that chip designers often overcompensate the inaccuracy of the models embedded in the tools by overdesigning the interconnects or employing overly
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tightened rules. This is an undesirable and expensive approach in terms of time and cost [51, 52].
An advanced model such as [53] considers time-varying temperature, however, temperature is assumed to be uniform across the entire long line. The relationship between the temperature profile (Joule heating) formation and current density (EM) is not addressed. To model the underlying physics of thermal effect correctly, temperature effect caused by Joule heating should be modeled through thermomigration. The authors in [54] present a hierarchical wire mortality conditions related to lifetime. However, the model does not take temperature gradients and thermomigration into account and complex numerical procedures are required in this method. Also, the effect of temperature on diffusion coefficient is often ignored or treated simplistically in many existing models [55]. Other filtering approaches exist for multi-segment interconnects in nominal temperature [56, 31]. These recent approaches in their core employ the model presented in [29] describing hydrostatic stress evolution which does not consider TM.
In current physical design practices and verification methodologies, lifetime checks, and thermal analysis are commonly done in different signoff steps without considering their true correlation. It is a common practice that critical current density and wire length are often determined by temperature-agnostic EM models and then combined with temperature rise threshold. However, they should be coupled and modeled jointly. Electromigration changes the resistivity and causes Joule heating. Joule heating, on the other hand, affects electromigration due to diffusivity (temperature rise or ΔT) and atoms motion due to thermomigration (temperature gradients or ∇T).
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Due to temperature agnostic electromigration models, two hazardous situations may occur: (1) in some cases, the models may wrongly scrutinize reliability in unfailing parts and consequently impose unnecessary design tightening; (2) in some other cases, the models may underestimate serious reliability problems causing unpredicted behaviors or catastrophic failures to occur. The existing models for mass transfer induced reliability evaluation are usually pessimistic in case of interconnect voiding and optimistic when extrusion occurs.
3.2.2. Existing Models
Blech’s model is devised for metallic wire aging induced by application of electric field and its relationship with mechanical stress. In this model, thermal aspects of aging are not considered. As a result, this model is not sufficient for a comprehensive reliability evaluation. To account for thermal effects, it is often employed with extra design rules enforced by thermal load (e.g. a threshold for ΔT) due to Joule heating [44].
Fig. 3.1 demonstrates that excluding thermal effects from material migration induced aging results in ever-increasing inaccuracy in reliability evaluations. Thermal effects caused by Joule heating influence stress evolution in advanced technologies more severely than before. Depending on the temperature distribution caused by ohmic heating, the final stress profile predicted by Blech-based models may have non-negligible errors. In the experiment shown in Fig. 3.1, global wires are layer 8 (M8) metal wires in 45nm and 10nm Intel’s technology interconnect stacks, with lengths of 192um and 48um, respectively. Local wires are layer 2 (M2) metal wires in 45nm and 10nm Intel’s interconnect stacks, with lengths of 44um and 15um, respectively. Even though by technology scaling jL product increases, in this experiment, jL is conservatively kept constant for the wires in both technologies.
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The wires are typical end-to-end straight wires extracted from technology-scaled interconnect stacks from IBM benchmark [57]. The wires are constructed with geometrical and material properties for copper, liners, cap and dielectric by Intel [58, 59].
location across wire location across wire
Figure 3.1: Impact of thermal effects on stress formation through technology scaling. The stress profile in (a) a global and (b) a local interconnect without (solid line) and with (dashed line) thermal effects.
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The global wire in 10nm technology experiences higher temperature rise and greater temperature gradients due to technology enforced requirements such as denser design, higher current density, lower dielectric constant and thermal conductivity. Blech’s model indicates that the wire will not suffer from voiding or extrusion. As it can be seen in Fig. 3.1 (a), Blech’s model predicts higher tensile stress (pessimistic) and lower compressive stress (wrong/optimistic) in the wires under a typical ∩ shape temperature distribution caused by Joule heating. This ever-increasing effect is more severe in advanced technologies. In Fig. 3.1 (a), thermal effect causes the anode to experience greater compressive stress that cannot be detected by the existing models. The finite element method (FEM) experiments reveal that Blech’s model does not assess correctly the overall reliability of global interconnects under thermal loads.
More interestingly, local wires are typically considered to be safe using Blech short length effect. However, for advanced technologies, they not only suffer from similar problems as global wires (e.g. higher current density and lower thermal conductivity), but technology scaling additionally depresses the electrical and thermal conductivity of copper wires with dimensions finer than copper mean free path. The higher electrical resistivity and lower thermal conductivity accompanied by higher current density greatly affect stress evolution. In Fig. 3.1 (b), local wires are both under the same condition (e.g. ambient temperature) with a typical ∪ shape temperature profiles. Tensile stress in the cathode of the wire in 10nm technology exceeds the critical stress for voiding and therefore a dangerous voiding is missed by simply Blech model-based filtering.
The test conditions (e.g. current density and temperature distribution) in our experiments are relatively conservative, whereas the wire can easily experience more acute temperature
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loads and gradients due to microstructure nature of metal [60, 61]. Nevertheless, our experiments indicate that not including thermal effect properly and simultaneously with electromigration may be the culprit for many unexpected behaviors and device failures [42, 43, 44, 62]. The technology-dependent data in our experiments setup are extracted from [58, 63].
The gap between the stress profiles when Joule heating is included and not included is much greater in more advanced technologies [64].