Experiment

The series expansions unfortunately have the undesirable effect of progressively under- estimating the channel current as the gate-source voltage is increased above the turn-off voltage. Reasonable accuracy was achieved when applied to devices with gate lengths a low as 4 µm, although this will have invariably resulted in non-physical parameter values. Much like the SPICE primitive, this model becomes unsuitable for medium and long channel devices, increasingly so for those with large negative turn of voltages.

2.3.3 Experiment

The impracticality of diffusing dopants to form sufficiently deep gate and channel regions and the poor quality of those formed through ion implantation has prompted the ubiquitous adoption of epilayers for producing SiC JFETs. The low current and voltage requirement of signal level JFETs circumvent the need for complex structures typically adopted for power devices [80] and allows channel and gate regions to be formed from single homogenous epilayers. Devices intended for use in IC applications are subsequently required to have lateral channels and top mounted contacts. Unsurprisingly, the typical structure of n-channel lateral depletion-mode (NLDM) JFETs found in the literature closely resembles Figure 2.12. Variations in electrical characteristics do arise however on account of the device dimension and the choice of epilayer doping concentrations.

Acceptable quality SiC wafers became commercially available toward the end of the twentieth century. Subsequently, Scozzie et al. were some of the first to publish experimental

characteristics of 4H–SiC JFETs, reaching temperatures as high as 400◦_{C[58,81,82]. While} their choice a buried gate structure is not compatible with IC fabrication the device operation is comparable to top gated variants. The nominal channel length, width and depth adopted were 5 µm, 1 mm and 0.2 µm, respectively. The buried gate epilayer was determined to have a net active Al acceptor doping concentration of 1.6 × 1018_cm−3 _{while the N donor} concentration in the channel was found to be 2.4 × 1017_cm−3_.

The quoted graphically extracted turn-off voltages measured approximately −6.5 V which agrees well with the one-dimension p-n junction theory for a step junction previously dis- cussed [58]. A pertinent observation, however, is that ratio of the gate and channel doping concentrations will result in a large portion of the applied voltage not appearing on the channel side of the junction, thereby degrading the intrinsic gain of the device. They were successful in attributing the non-linear variation of the channel current with temperature to the combined influence of dopant ionisation, electron mobility and gate-channel p-n junc- tion contact potential. The resulting saturation currents for zero applied gate-source bias, i_DSS, are presented in Figure 2.21. Using the observed value of i_DSS at room temperature, a corresponding value for the Hall effect mobility and a basic two level donor model they were able to estimate the donor ionisation as approximately 69 %.

While long identified as being suitable for use at high temperature and in environments exposed to high doses of radiation, attention for many years following became largely focused on exploiting SiC for high voltage power electronics applications. The maturity of growth and processing techniques and the emergence of a niche yet high profile market for resilient electronics has caused a resurgent interest by a small number of groups. The longest standing and most high profile contributors have been Neudeck et al. at the National Aeronautics and Space Administration (NASA) Glenn Research Center (GRC), who first presented SiC JFETs back in 2000 [83]. Case Western Reserve University (CWRU) have collaborated

0 10 20 30 40 50 200 300 400 500 600 700 iDSS / mA T / K Figure 2.21

Experimental channel drain-source saturation current at zero applied gate-source voltage, i_DSS, for a n-channel buried gate JFET with Al doped gate concentration of 1.6 × 1018cm−3, N doped channel concentration of 2.4 × 1017cm−3, and channel length, width and depth of 5 µm, 1 mm and 0.2 µm, respectively. Reprinted [adapted] from [58].

0 0.5 1 1.5 2 0 10 20 30 40 50 1 hour 3007 hours iDSS / mA vDS/ V Figure 2.22

Drain current for zero applied gate-source bias, iDSS, of a packaged 6H–SiC n-channel lateral depletion mode JFET with 200 µm wide and 10 µm long gate, measured during the

1st _{and 3007}th _{hour of continuous operation at 500}◦_{C. Reprinted [adapted] from [84].} with NASA GRC since 2005 with the goal of developing SiC ICs for remote sensing in high temperature systems. The perceived superiority of 6H–SiC during this time led to its adoption by both groups, although more recently they have made the switch to 4H–SiC [2]. The NLDM devices produced by each group closely resemble Figure 2.12 with gate, channel and body epilayers having nominal doping concentrations of 2–5 × 1019_cm−3_{, 1 × 10}17_cm−3 and 2 × 1015_cm−3_{, respectively, with thicknesses of 200 nm, 300 nm and 7 µm, respectively.} Drain and source contact implants (> 1019_cm−3_{) were included to achieve low resistance} ohmic contacts and reduce the series resistance.

Their most notable achievement to date is a demonstration of 10 000 hours of continuous operation at 500◦_{C[4,84]. During this time critical device parameters were shown to degrade} by less than 10%. The channel current for a 6H–SiC JFET after a 1 hour burn-in and 3007 hours (approximately 4 months) of exposure is presented in Figure 2.22 [84]. Such changes, while small, can significantly impact circuit operation and so should be accounted for in any proposed circuit designs.

While their experimental results have proved the suitability of SiC JFETs for high tem- perature applications, little effort has been placed on developing accurate mathematical models suitable for implementation in circuit simulators. Each group continues to rely on either the primitive model provided by SPICE or a crudely modified version of Shockley’s original analysis [83, 85, 86]. Figure 2.23 demonstrates the noticeable discrepancy between the simulated and experimental values. More recently NASA GRC have identified the im- portance of body bias on channel current and have provided analogies with a long channel MOSFET SPICE primitive model; however, this still remains less useful than the Ding model previously described, is highly non-physical and can only achieve agreement with experiment over narrow region of operation. In the latter case an attempt was made to indirectly ac- count for the effect of substrate biasing through use of a modulated channel thickness. This however fails to account for the influence of channel potential on the bottom gate. In both

0 0.02 0.04 0.06 0.08 0.1 0.12 0 5 10 15 20 25 30 vGS/ V 0 −2 −4 −6 −8 iDS / mA vDS/ V Figure 2.23

A comparison of experimental 6H–SiC n-channel lateral depletion mode JFET characteristics (points) and simulations with the SPICE primitive compact model (lines).

Reprinted [adapted] from [83].

cases the absence of suitable thermal parameter models requires that separate device models be created for use at each temperature, thereby greatly inconveniencing the user and limiting the range of analysis that can be performed.

Their 6H–SiC devices have also been proven stable for over 4600 hours (approximately 6 months) of testing within low-earth-orbit on the international space station [87].

Active development of signal level SiC JFETs for hostile environment applications has up until recently been limited to NASA GRC, CWRU and Newcastle University (NU)’s Active Sensor Structures for Extreme Environments (ASTRO) group. Lately, however, Lien et al. have fabricated their own version of devices based on the specification outlined by NASA GRC and CWRU but using 4H–SiC. Their work so far has been limited to demonstrating single working devices but have achieved successful short term operation at 600◦_{Cin air [8].} Example output characteristics for a device with gate width and length of 100 µm and 10µm, respectively, at 25◦Cand 600◦Care presented in Figure 2.24, exhibiting a maximum change in channel current in excess of 80 %. Unfortunately, the lack of data at intermediate temperatures provides limited insight into the direct current (DC) properties of the devices. The product of a device’s transconductance, gm, and its output resistance, ro, is termed the intrinsic voltage gain, gmr_o and is a transistor figure of merit defining the maximum achievable voltage gain for a given bias. An illustration of the observed transconductance at zero gate-source voltage, normalised to channel width, and the corresponding intrinsic voltage gain are presented in Figure 2.25 [8], where the average value of output resistance in saturation is believed to have been used. For the chosen device dimensions they observed the intrinsic voltage gain drop from 81.5 to 57.2 between 25◦_{C to 600}◦_{C, representing a} decrease of 30 %.

A reliability study showed that the transconductance changed by 3 % over an 90 hour period at 540◦_{C; however, a similar test at 600}◦_{Cresulted in a 30% change after only 1 hour} [8]. It is likely that contact degradation is responsible for this drastic change with oxygen

0 0.5 1 1.5 2 0 5 10 15 20 vGS/ V 0 −2 −4 −6 iDS / mA vDS/ V (a) 25◦_C 0 0.5 1 1.5 2 0 5 10 15 20 iDS / mA vDS/ V (b) 600◦_C Figure 2.24

Experimental output characteristics of a 4H–SiC n-channel lateral depletion mode JFET with gate width and length of 100 µm and 10 µm, respectively, measured at (a) 25◦_Cand

(b) 600◦_{C. Reprinted [adapted] from [8].}

0 1 2 3 4 5 6 0 100 200 300 400 500 600 30 40 50 60 70 80 90 gm / S m − 1 gm ro / V V − 1 T /◦C Figure 2.25

Experimental transconductance, gm, and corresponding intrinsic gain, gmro of a 4H–SiC n-channel lateral depletion mode JFET with gate width and length of 100 µm and 10 µm,

respectively, as a function of temperature, T. Reprinted [adapted] from [8].

from the atmosphere diffusing through the metal to the metal-semiconductor interface. The results suggest practical limits are placed on SiC devices that have not been properly designed to withstand high temperatures. The reported off-state current at a gate-source voltage of −9 V was found to increase from 6.31 × 10−9A to 1.97 × 10−7A in the same temperature range [8]. While small in comparison to convention semiconductors they remain far in excess of theoretical values achievable by 4H–SiC.