Experimental Protocol - Data Collection Methods and Procedures

3. Data Collection Methods and Procedures

3.1.4. Experimental Protocol

∆

I/2 + I /2₁ I/2 − I /2∆₁

∆

I/2 + I /2 ∆

∆ ₀

I/2 + I /2 I/2 − I /2∆ ₀

2 I/2 − I /2₂

Figure 3-36: Four-quadrant bipolar Gilbert multiplier.

3.5. Circuit Structures 83

+−

∆V_in

∆ out ∆ out

I/2 + I /2 I/2 − I /2

∆ in

I/2 + I /2 I/2 − I /2∆ in

Figure 3-37: A simple MOS version of the Gilbert multiplier.

use bipolars in our design due to their size, so we need an mos version. Much eort has been invested over the years in designing multipliers in mos. These topologies fall into two basic categories: approaches based on the Gilbert multiplier [61, 62, 63] and approaches based on the so called quarter-square technique [64, 52, 65, 66]. In the approaches based on the Gilbert topology, the pre-distortion circuit is omitted entirely, and the remaining core of four bipolars is replaced with mos devices. The resulting circuit has a signicant amount of nonlinearity, and much eort is made to cope with it. The quarter-square technique is based on the following observation:

V

2= (

V

2)²^;(

V

1^;

V

2)² (3

:

75) and hence a multiplier can be realized using two dierential squarers, of which there are a plethora of voltage in current out versions.

However, all of these approaches are much more complicated and area-consumptive than we can aord. It was settled upon to use a mos version of the four-transistor Gilbert core, shown in Figure 3-37, due to its extreme simplicity. Starting as before, we can derive the DC transfer characteristic of the mos Gilbert multiplier above threshold. We normalize all of the dierential variables:

I

I ;

V

;

out=

I

out

I

⁽³

:

76)

where

V

I

(

C

W=

L

) (3

:

77)

;

out1 (3

:

78)

-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1

η β out

β = 1 β = 0.75

β = 0.5 β = 0.25

β = -0.25

β = -0.5 β = -0.75 β = -1

Figure 3-38: Normalized input dierential voltage to output dierential current transfer char-acteristic of the MOS multiplier.

The normalized output is

out=

2 where

; 1+2

^;^q¹⁺₂

^p1 +

² if

² ¹⁺₂

1+2

^q¹⁺₂ ⁽³

:

79)

: 1^;

^;^q¹^;₂

;

^p1^;

² if

² ¹^;₂

; 1^;

^q¹^;₂ ⁽³

:

80) The family of curves dened by these relations is shown in Figure 3-38. While this function has the appropriate qualitative behavior required of a four-quadrant multiplier, it does exhibit substantial nonlinearity. In the case of the source coupled pairs used in our transconductors, the input signals were small (typically ^j

V

i^j 1

V

), so we could have made the gates long enough to accommodate whatever input linearity we desired. The multipliers, though, will potentially need to operate with a wide variety of dierential input voltages, depending on the voltage encoding of the position signals. For example, with a 6464 system and a voltage encoding of 100

mV

per pixel, the required range of the multiplier is6

:

V

. On the other hand, we can restrict the maximum and minimum voltages of the position to lie in a 1

V

region just as easily. Hence, the input range of the multipliers

V

r was arbitrarily set at 1

V

. Since the common mode current of the input dierential currents is 10

A

at this stage of the processor,

3.5. Circuit Structures 85 this required a

W=L

= 1 = 8

m=

m

. The full circuit implementation of the rst layer of multiplication is shown in Figure 3-39. The resulting output currents from each multiplier is summed and mirrored with a cascoded current mirror into the second stage of multipliers, shown in Figure 3-40.

Since each multiplier potentially provides a maximum dierential current of 2

I

with a common-mode current of 2

I

, one could imagine that the output dierential-mode would have a maximum of 4

I

with a common-mode of 4

I

. In fact, this is not the case because

E

x and

E

y are orthogonal linear combinations. The output current represents

p

= (

x

E

x+(

y

E

xE

x +

yE

y. Normalizing and referring back to the

s that form (

E

;E

y), we note that (

x; y;

;

4) is conned to a 6D unit hypercube, and we would like to nd max(

p

) over this hypercube. From linear programming [67], we know that if a solution exists, it lies at the vertices of the hypercube. Hence, we can evaluate

p

at the vertices to nd the maximum.

Examining the allowed (

E

;E

y) due to the vertices in

-space, we note that the only allowed (

E

;E

y) vertices are (0

:

;

:

;

1) but (

E

;E

y)⁶= (1

;

1). Given the reduced set of (

E

;E

y) vertices, clearly max(

p

) = 1 and not 2. Hence, while the output common current in the sum is now 4

I

, the maximum output dierential current is half of that.

In the second layer, we take the output from the rst layer and transduce it to voltage.

This dierential voltage is then applied to the inputs of the multipliers. To accomplish this transduction, the simple I/V converter based on triode connected transistors is used, as shown on the left of the gure. In the triode region, the I/O characteristic of a transistor becomes:

I

^h2(

V

gs^;

V

ds^;

V

_2dsⁱ (3

:

81) and this is true when the gate drive

V

gs^;

V

> V

ds. Since the gates of thepmos transistors are grounded, this condition is always satised. If we drop the quadratic term in Equation 3.81, we can view a transistor operating in the triode region as a resistor of value:

R

= 1

(

V

gs^;

V

t) (3

:

82)

Each of the leg currents of the dierential input currents

I

+ = 2

I

+ 2

I

;I

^; = 2

I

^;2

I

p is passed through a triode transistor with resistance

R

and hence

V

p =

RI

+^;

RI

^;=

R

I

+ 2

I

p)^;

R

I

^;2

I

p) = 4

R I

p (3

:

83) And this

V

p is input to the second layer of multipliers, which are identical to those of the rst layer. Since the dierential current is restricted to half of the bias, then ^j

I

p^j

< I=

2 and the maximum voltage swing is

V

p = 2

RI

The diode at the top of the triode transistors is sized

W=L

= 0

:

5 = 6

m=

m

to shift the common mode of the output down into the input common-mode range of the multipliers. The common-mode of the input current is 4

I

= 20

A

, and hence the voltage drop across the diode is

V

t+^p4

I=

(

W=L

) 3

V

. The source voltage is

V

d =

V

dd^;3

V

= 7

V

and hence the

gate drive is

V

d^;

V

. Matching the maximum output of the I/V converter of 2

RI

where

I

= 5

A

to the one volt input range of the multipliers requires

R

= 100

k

. With a gate drive of 6

V

, this would require a device size of

W=L

= 1

=

12. However, at the large gate drive we are using, the transistors exhibit a factor of 2 mobility reduction due to mobility degradation [68].

This increases the resistiveness of the devices, so only half the length is required. Hence, the triode transistors were sized at

W=L

= 1

=

6 = 6

m=

m

to provide the appropriate resistance.

The two dierential current outputs from the second layer of multipliers are the output error channels

e

x and

e

y respectively, which are summed up the column in KCL and sent o-chip. Even though the I/O transfer function of the analog processor is multidimensional (there are 10 dierential inputs), we can nd a transfer characteristic from the transconductor inputs to the output of the second layer of multipliers by for example driving

E

y maximally (i.e.

1 =

2 =

3 =

4 =

=

4). Since

E

x and

E

t are orthogonal linear combinations to

E

y, they are zero under this condition. A mesh plot of the resulting DC transfer curve is shown in Figure 3-41. (

y

0) is denoted by the normalized variable

while

E

y is denoted by the normalized variable

. Taking slices in the

direction (Figure 3-42) shows the desired quadratic behavior with

E

y, while slices in the

direction (Figure 3-43) shows the transconductor behavior with (

y

0).

In document Validation and uncertainty of inverse dynamics analysis applied to high acceleration movements (Page 65-68)