Explicit Phases

The first idea is to model process phases in an explicit way as shown in Figure 6.3. This is exactly what happen to processes: different phases, each one effectuating memory requests with own rate, interleave among them. The idea is to catch the frequency wherein a process passes from a generic phase to another one.

think wait send wait rts rst

Figure 6.3: The behaviour of a client exploiting a think phase followed by a send one.

6.3. Process Phases Modelling 87

An example on how this can be achieved in PEPA is reported below. Basically, we change the definition of client in such a way will be also possible to pass from a phase to another one.

Cthink

def

= (request, rrequestt).Cwaitt + (send , rts).Csend

Csend

def

= (request, rrequests).Cwaits + (think , rst).Cthink

Cwaitt def = (reply,>).Cthink Cwaits def = (reply,>).Csend

Assume the two phases involved in Figure above, then frequencies rts and rst

are easily found reverting their period: rts = 1 ft· TPt rst = 1 fs· TPs (6.4) Apparently, this way to operate has a problem. As already explained above, we are effectuating estimations on the base of the sequential code inspection so the length of phase periods are evaluated only considering the number f of faults and the mean time between two consecutive memory requests (TP). The length of a phase is crucial in our treatment because

it influences directly the rate of some actions. Of course, problems arise when more processes are in execution because the impact of the under-load memory access time.

Consequently, the rate estimations 6.4, that are found statically, can dif- fer a lot from the effective ones. So phase periods should not be evaluated only considering the sequential version, i.e. f _{· T}P, but have to include the

impact of RQtoo. This can be done in various ways, a solution is to adopt an

iterative approach. However, we have to keep in mind that we want to keep low the complexity to found RQ, so we prefer to introduce an approximation

respect to complex procedures. Therefore, the length of phases can be esti- mated using the base memory access latency ta0 that can be derived easily

at compilation time. Considering that, we set the rates in the following way: rts =

1 ft· (TPt + ta0)

rst =

1 fs· (TPs + ta0)

(6.5) As already explained in Section 2.3.2, basically ta0 is the sum of terms:

the latency Ls of the server in case no conflicts are taken into account and

the base network latency Tnet = Treq+ Tresp:

ta0= Ls+ Tnet

The idea is to substitute the base latency Lsof the server with the under-

load memory access latency RQserver found with PEPA in order to obtain no

more ta0 but RQ:

RQ = RQserver + Tnet

Results and comments Figure 6.4 shows the under-load memory access latency RQ of the simulation (SIMULATOR), the previous version (PEPA-

WA) and the new version with explicit phases (PEPA-EP). Figure 6.5 shows the absolute and relative error.

100 150 200 250 300 350 400 200 300 400 500 600 700 800 RQ − clock cycles Tp − clock cycles SIMULATOR PEPA−WA PEPA−EP

6.3. Process Phases Modelling 89 0 10 20 30 40 50 60 70 200 300 400 500 600 700 800

Absolute Error − clock cycles

Tp − clock cycles

PEPA−WA PEPA−EP

(a) Absolute Error

0 5 10 15 20 25 30 35 200 300 400 500 600 700 800 Relative Error Tp − clock cycles PEPA−WA PEPA−EP (b) Relative Error

We can see that the relative error (we call it φ) of the new version (PEPA- EP) is higher than the error of the previous version (PEPA-WA). This is due to the approximation that we introduce in the evaluation of phases periods. Considering that, we can also affirm that the error depends by the difference between ta0 and RQ hence it will be greater if their ratio grows:

RQ

ta0 ↑=⇒ φ ↑

However, the error in this new version is almost constant in all the range and no more with enormous changes as before.

The potential advantage of this technique is that we believe that it could be used in order to model processes not always working. In fact, it is sufficient to pass from the think phase to a stopping one where no memory requests are generated. It is important to notice that the accuracy still depends by the ratio RQ

ta0.

How this can be achieved in PEPA is shown in the following code: Cthink

def

= (request, rrequestt).Cwaitt + (stop, rts).Cstop

Cstop def = (think , rst).Cthink Cwaitt def = (reply,_>).Cthink

First of all, we recall that processes with efficiency ξ < 1 are not bottlenecks so their effective service time TS is equal to the inter-arrival time TA. Thanks

to the structured parallel approach, we are able to estimate the effective service time of a process looking at TA that is a well know input parameter.

Considering that, the rates to switch from a generic phase to another one should be setted in this way:

rts = 1 Tsid = 1 ft· (TPt + ta0) rst = 1 TS− Tsid = 1 TA− Tsid

If we apply the formulas above to the example of the Section 6.1.2, we have that the emitter states the following parameters:

6.3. Process Phases Modelling 91

Tsid ' Tsend =⇒

(

rts = _Tsend1

rst = _TA−T1_send

Unfortunately, this scenario has not been simulated yet so we have no results about this hypothesis, but it belongs certainly to future works.