This dis sertation documented the application of the methodology to the KDLX RISC processor. It was validated with the laser and heavy- ion testing, which is important, but for this dissertation to be complete, how the methodology can be applied to other classes of complex digital systems must also be shown.
1. The Standard-Cell Application Specific Integrated Circuit(ASIC) 4
The first alternate implementation considered is the standard-cell ASIC. Because this is a standard-cell design, the designer has the same information available from the
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parametric test results of the foundry run, the extracted layout, and the gate- level hardware-description language (HDL) definition of the design. Thus, the approach is the same as the KDLX to determine the SET generation probabilities. The analog propagation and clock-edge effects modeling are also the same. The difference between the standard-cell ASIC and the KDLX processor is that the ASIC does not have an instruction set. This means that the instruction-based register-usage analysis approach does not apply. Thus, instead of determining the datapath and the ε1 transitional probability for each instruction, these must evaluated for each functional mode. The total effective device cross-section is then determined by the equation:
σdevice = Σ σn* Dn , n = 1 to the total number of modes, where (6.1) σn = mode-dependent cross-section for mode n,
Dn = duty cycle of state n.
2. Field Programmable Gate Array (FPGA)
The next alternate implementation considered is an FPGA. This is fundamentally different from the standard-cell ASIC because the engineer typically will not have the parametric test results of the foundry run or a SPICE transistor- level model of the logic modules. However, the designer will have a high- level description of the design, as well as a synthesized logic- module description. It is also likely that the engineer has some SEU data on the FPGA logic modules [47]. Assuming that there is SEU test data on the logic modules, the problem becomes determining the functional- mode-dependent cross- section. This requires a determination of the number of logic modules used for each functional mode. The total device cross-section is then determined using equation 6.1.
3. Off-the -Shelf Processor
An off-the-shelf processor is the next implementation considered. In this case, the only information likely to be available is an instruction-set architecture (ISA) description of the processor. The information contained in an ISA description may be similar to the information in a full HDL description of the microarchitecture, except that the ISA
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While it is true that an ASIC can be a processor, here an ASIC is defined as a complex digital system that does not contain an instruction set.
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description will be missing the hidden memory elements that are included in the HDL description. Examples of hidden memory elements in the KDLX are the pipeline memory elements, the ALU-buffer memory elements, and the data input/output buffer memory elements. These hidden memory elements may create a very big difference between the ISA description and the HDL microarchitecture description. These hidden elements contribute to the effective cross-section, but are not apparent in looking at the ISA description of the processor.
The approach for the processor focuses on determining the instruction-dependent cross-section using a combination of what is known from the ISA description and what can be determined about the microarchitecture from SEU testing. The procedure is as follows:
1. For each instruction type, determine the sensitive memory elements using the ISA description.
2. Add a variable to depict the additional hidden sensitive memory elements for each instruction to the result in #1.
3. Create a test program for each instruction type to determine the mode- dependent cross-section associated with that instruction type. Predict the cross- section of the test program using #1 and #2.
4. Create a (or use an existing) program that uses many different instructions. This is the validation program. Predict the cross-section using #1 and #2.
5. At a high LET (to insure the best statistics), run all programs to determine the saturated cross-sections for each program.
6. Using the test program with the largest saturated cross-section, test the processor at lower LETs to obtain a cross-section versus LET curve. The other test programs should follow this same cross-section versus LET trend.
7. Determine the hidden number of memory elements for each instruction by comparing the resulting saturated cross-sections with the cross-sections that were predicted in #3.
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8. Update the instruction-dependent cross-sections by including the contribution of the hidden memory elements.
9. Compare the measured cross-section of the validation program to the updated predicted cross-section. If the two agree, the predicted instruction-dependent cross-sections will be validated.
4. Off-the -Shelf ASIC
The final implementation considered is an off-the-shelf ASIC. In this case, the device is not a processor, and the only information typically available is a block diagram from the data sheet, which may be significantly different from the actual architecture. As before, it is necessary to determine the cross-section for each of the operational modes of the device. Each functional mode of the device should be tested at a high LET to determine the relative cross-section of each mode. Then, as with the off- the-shelf processor, the cross-section versus LET curve is determined by testing at lower LETs with the device operating in the functional mode with the largest cross-section. The total effective device cross-section is determined by using equation 6.1.