Fabrication

We used the clean room facilities from Waseda University at the Nanotechnology Research Center (NTRC) that are located in building 120-5. NTRC belongs to a collaborative research project supported by different universities, industry members and governmental associations from Japan called the “Nanotechnology Platform Japan”

(NTPJ). It is administered by the Minister of Education, Culture, Sports, Science and

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Technology (MEXT). The main idea behind this project is that different universities and companies share their cutting edge equipment between all members to provide the fastest way to solve an urgent problem in science and technology [40]. In Waseda University, there are different classes of clean rooms that range from Class 100 to Class 10000 and also, there are chemical rooms, electrical laboratories and specialized equipment for nanotechnology research.

The procedure for fabricating the chips at NTRC is summarized in the following list and each step is described in detail in the subsequent paragraphs.

1. Dicing of the wafer into chips of 2 × 2 cm². 2. Cleaning of the chips

3. Resist coating of the chips

4. Electron-Beam Lithography exposure 5. Development

6. Etching of the pattern 7. Resist removal

We purchased 5 inch SOI wafers from Suzuki Shokan that each one has a Si thickness of 250 nm ±15 nm. A BOX thickness (SiO2) of 2000 ±50 nm and a handling layer of 525

±15 microns. Therefore, all of our devices were designed for a 250 nm Si thickness. The BOX thickness is important when designing the grating coupler and other parameters as will be discussed in the following chapters.

1. Dicing of the wafer

As we produce device by device, we first diced the wafer into smaller squares of 20 × 20 mm² with a dicing machine. To protect the wafer from flying particles during the dicing process, we first coated the whole wafer with a protective resist layer of TSMR.

After the dicing was completed, about 32 chips per wafer were obtained as shown in Figure 1-10. During the dicing process, a blue adhesive sheet is used to fix the wafer and avoid any movement during the process. In order to remove the blue sheet, a heating plate set to 120 °C is used as the adhesive property is lost at that temperature, so we can safely take a single chip.

Figure 1-10 Diced wafer 5 inches

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After obtaining individual chips, the TSMR resist was removed with acetone in an ultrasonic bath for 5 minutes. Then, we cleaned the surface of the chip by sweeping it with a bemcot® [41] wiper soaked in acetone. Then, the chips were immersed in acetone followed by isopropanol for 5 minutes in an ultrasonic bath for each chemical. We then thoroughly rinsed with deionized water for 5 minutes and finally spin dried the chips.

With this procedure we guaranteed that the surface of the chip was free of any small particle right before exposure.

3. Resist Coating

Immediately after the cleaning process, the chips were coated with the positive resist ZEP520A from ZEON chemicals with a spin coater and three different spin speeds. First, 300 rpm for 3 seconds, then 60 seconds at 3000 rpm and finally an end slope for 5 seconds.

With that spin curve, we are supposed to get a resist thickness of 400 nm according to the data sheet [42]. After the spin coat process, the chips were baked at 180 °C for 3 minutes.

Figure 1-11 ZEP520A Spin Curve [42]

4. Electron-Beam Lithography

The fourth step consists of exposing the resist to create our device patterns using Electron-Beam Lithography (EBL), specifically using the ELIONIX ELS-7700W. We first mounted the chip on the ELIONIX chip stage and then inserted the stage into the EBL system. We set our working range to an area of 300 μm × 300 μm with 60,000 dots.

Then, we tuned the beam current with the help of the Faraday Cup to obtain the required current of 100 pA with an accelerating voltage of 75 kV and dose time of 0.4 μs. After that, we fixed the focus and stigma of the different lenses that constitute the EBL system.

These two steps are repeated until there are no changes in terms of beam current, focus and stigma. When there are no more changes, the field correction is applied to fix some stitching problems and the final step is to begin the exposure. The EBL system is shown Figure 1-12

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Figure 1-12 (Left) Chip ready to be exposed (Right) EBL system

As we can achieve direct pattering without using optical masks, we have a lot of freedom to make rapid changes to the design of the device. We design our devices with a computer aided design (CAD) software and then translated to a CEL file which is the type of files that the ELIONIX machine can handle. For our case, we use a positive resist so we have to expose the parts of the chip that we want to etch (remove). For example, if we want to obtain two waveguides separated by a square, we have to expose the white area as shown in Figure 1-13. The un-exposed parts are not etched and are protected with the resist during the subsequent steps.

Figure 1-13 (Left) CAD file (Right) SEM image of a fabricated device

5. Development

After the EBL exposure, the chips were developed with the high resolution developer ZED-N50 for 1 minute and slow agitation, and then, rinsed with ZMD-B for 30 seconds and finally blown dried with nitrogen. All chemicals are from ZEON Company and they were used as received. After development, the chips were stored overnight at room temperature.

6. Dry etching

The sixth step consists of removing the unwanted silicon using Inductive-Coupled Plasma Reactive Ion Etching (ICP-RIE SAMCO) machine as shown in Figure 1-14. RIE can use a variety of gases to etch the silicon, and we used SF6 gas at low pressures and

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powers to obtain smooth sidewalls. The etching time was 2 minutes and 6 seconds, with a bias power of 240 W and a RF ICP power of 100 W at a constant 1.0 Pa pressure.

Helium was used as a refrigerant gas with a pressure of 12 × 10² Pa. The process consists of first filling up the gas pipe line with the gas that we want to use. Then, we clean the reaction chamber with an oxygen cleaning step for 10 minutes. Finally, we insert our chip and etch it with 20.0 sccm of SF6.

Figure 1-14 ICP-RIE

7. Resist removal

The final step is to remove the remaining ZEP520A resist with ZDMAC from ZEON chemicals by immersing the chip for 8 minutes in an ultrasonic bath in this chemical, and then, rinsing with deionized water and spin drying it. After this step, the chips were completed, and no additional cladding was deposited on top of the chip. The summary of the fabrication flow is represented in Figure 1-15, starting from the second step.

Figure 1-15 Fabrication process of the devices

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Even though the fabrication process is relatively simple, there are several parameters that have to be optimized such as spin speed of ZEP520A to achieve a specific thickness, dose time and current for the EBL process, etching gas and etching powers for the ICP-RIE. We investigated the main effects of some variables in the fabrication process and in the following paragraphs we show the different problems that we faced and how to overcome them.

First, we analyzed the effects of dose time and resist thickness. When the dose time was too less, or the resist thickness was too thick, the structures were not perfectly achieved as shown for a line-and-spacer in Figure 1-16. From the Scanning Electron Microscopy (SEM) image after the etching process, we can see that there is some silicon left in between the lines due to the lack of exposing time. On the other hand, if the dose time is set too high, overexposing occurs resulting in wider spaces and rounded corners of the design due to the called proximity effect of EBL. Also, if the resist layer is too thin, it may collapse during the subsequent processes. Therefore, the optimum thickness of 400 nm is required to obtain good results.

Figure 1-16 Line and spacer with an inadequate dose time. The image shows the case for a dose time of 0.3 μs

After optimizing the dose parameter, we focused on the etching step. First, we used CHF3 as the etching gas and we obtained very dirty surfaces due to the fact that during the etching process, the powers were too high around ICP 400 W and BIAS 300 W so the resist was destroyed as shown in the left of Figure 1-17. By changing the gas to SF6, we could obtain a much cleaner surface as seen in the right of the same figure. Nevertheless, the powers were still too high ICP 200 W and BIAS 240 W, so the waveguide sidewall had large corrugations. Finally, we found the optimum values for the powers to be ICP 100 W, and BIAS 240 W.

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Figure 1-17 SEM images for (left) CF4 gas and (right) SF6 gas with high powers

The most problematic step was EBL. As it is known, EBL works by exposing a specific area in the chip, and then, moving the chip stage to the next area to be exposed. Therefore, there are some problems that can occur in the boundary regions between each exposure area. The most common ones are either having some resist left, or a rotational shift in between exposing areas. They are also referred to as stitching problems and illustrated in Figure 1-18. In the left we can see that there is some silicon left in the border of each exposure area, and in the right one we can see that the waveguide is not perfectly straight as there is some unwanted shift. A partial solution to the first problem is to overlap the CAD elements at the boundaries, at the expense of obtaining instead an overexposed structure. Nevertheless, the losses of such overexposed device are less than the one without overlapping. For the second problem there is no solution, other than trying to keep the chip stage movement as less as possible by designing small devices and short waveguides. When this is not possible, the power budget has to be large enough to still be able to get a strong signal across the waveguide.

Figure 1-18 EBL stitching problems (left) Resist remained and (right) mismatch of the stage

Another problem that we also encountered was when the developing time was not optimized. There are two main issues that are stirring agitation speed and time. We observed the formation of cracks from the resist that expanded from the corners of the design as shown in the left of Figure 1-19 when the developing time was too long. On the other hand, when the stirring agitation was too fast, the nano waveguide structure was

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destroyed as shown in the right. The way to solve this problem was to carefully agitate the chip during development so that the speeds were low. It is important to say that we performed the agitation by hand. We found that the most adequate developing time was 60 seconds and 25 seconds to rinse at room temperature and gentle agitation.

Figure 1-19 Developing problems (left) Formation of cracks (right) destruction of the pattern

After optimizing the fabrication process for producing photonic devices we could achieve very precise designs and very clean sidewalls with acceptable losses. A sample of an optimized line and spacer is found in Figure 1-20.

Figure 1-20 Optimized line and spacer

Nevertheless, even after optimization of the EBL and the ICP-RIE processes, the final size of the structures is reduced. The reduced amount is greatly affected by either the focus, stigma of EBL, resist thickness and gas pressure from ICP-RIE. Therefore, it is difficult to obtain exact and precise results down to the nanometer range, and even though our devices exhibited a similar performance, their exact responses varied from chip to chip. Fortunately, our designs have a certain tolerance to fabrication errors because we do not require precise resonant wavelengths as we are interested in the relative shift of the resonant wavelength from its starting position. Nevertheless, it is important to know the order of deviation to correctly design our systems, either by compensating with a bigger CAD structure, or by readjusting the design parameters of the devices.

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Unfortunately, measuring this error directly with a SEM tool is not precise as the stigma of the machine can change the measurement value in the magnitude of tenths of nanometers. So, in order to get an estimation of the discrepancy between CAD and fabrication, we used a semi-periodically structure of different shapes and sizes, and fitting the CAD shapes to the fabricated device, we are able to quantify this diversion. By fitting both images as shown in Figure 1-21, we remove the problem of the inaccurate SEM measurement method. From the CAD (red squares) superimposed on a SEM image, we can see that the etched holes are actually a bit bigger, especially around the corners.

Depending on the shape, the actual variations vary, but we can conclude that there is up to 40 nm variation in any direction. This variation affects our waveguides. For example, a 500 nm CAD design, would result in an actual waveguide width of about 440 nm, which corresponds to a shrinkage of 30 nm per side of waveguide.

Figure 1-21 A SEM image with the CAD design imposed to measure the fabrication tolerances

Next, to measure the height of the silicon layer after all the processes, we etched a large area of about 15 × 20 μm² and then used the KLA-Tencor machine to measure the height profile before, during and after the large etched area. We found out that the silicon height is about 250 with minor variations which are in close relation to the etching time of 2 minutes and 6 seconds of the ICP-RIE process.

With this optimized process, we fabricated the devices that are going to be presented in the next chapters. In the next section, we describe our experimental setups used through the rest of the thesis.