The majority of scanner related programmable logic functionality is contained in the FLEX PLD, an Altera EPF6024AQC208-3 device. Device programming is handled exclusively by the CPU. On each cold boot the CPU reprograms the FLEX devices from an image stored in it's FLASH. As such a firmware download of a new FLEX image is required to permanently upgrade the PLD code.
The functional components of the programmable logic are discussed in the following subsections. Polarity of operation can be inferred from bit names and use of preceding slash for inverted logic bits.
Note that ports A-F are reloaded with default values at time of CPU reset and remain in the default state until SCANNER_RESET has been cleared and new values are written by the firmware. Defaults for port F and all other registers are invoked at power up only.
PORT A
Bit Name R/
W
Def. Description
0 trans_enable R/W 0 Transverse motor enable – low blocks trans motor pulses and forces Centent drive to standby current level.
1 /trans_fwd R/W 0 Transverse motor direction control.
2 /shutter_open_ctrl R/W 1 Shutter solenoid control.
3 trans_lsw_override R/W 0 Transverse limit switch override – prevent limit switch contact
4 long_enable R/W 0 Longitudinal motor enable – low blocks trans motor pulses and forces Centent drive to standby current level.
5 /long_fwd R/W 0 Longitudinal motor direction control.
6 long_lsw_override R/W 0 Longitudinal limit switch override – prevent limit switch contact from blocking step pulses at hardware level
7 /collimator_open_ctrl R/W 1 Collimator solenoid control.
PORT B
PORT C
Bit Name R/
W
Def. Description
0 /trans_front_lsw R N/A Transverse front limit switch position.
1 /trans_back_lsw R N/A Transverse back limit switch position.
2 /long_foot_lsw R N/A Longitudinal foot limit switch position.
3 /long_head_lsw R N/A Longitudinal head limit switch position.
4 trans_count_eq[0] R N/A Set when transverse step counter equals zero.
5 long_count_eq[0] R N/A Set when longitudinal step counter equals zero.
6 /shutter_open_sense R N/A Shutter limit switch position.
7 /collimator_open_sense R N/A Collimator limit switch position.
Bit Name R/
W
Def. Description
0 /long_rev_pos R N/A Patient positioner (joystick) input.
1 /long_fwd_pos R N/A Patient positioner (joystick) input.
2 /trans_rev_pos R N/A Patient positioner (joystick) input.
3 /trans_fwd_pos R N/A Patient positioner (joystick) input.
4 /hvps_ac_relay R/W 1 Enable AC power to X-ray HVPS.
5 /motor_fail_enable R/W 1 Arm logic to shutdown scanner if OMI inputs not sensed.
6 ags_enable R/W 0 Enable detector automatic gain control feedback circuit.
7 /motor_power R/W 1 Enable 24VDC to the stepper motor drives (a.k.a. Centents).
PORT D
PORT E
Bit Name R/
W
Def. Description
0 flex_max_i/o_[0] R/W 0 Output signal to MAX PLD (diagnostic use only).
1 flex_max_i/o_[1] R/W 0 Output signal to MAX PLD (diagnostic use only).
2 flex_max_i/o_[2] R/W 0 Output signal to MAX PLD (diagnostic use only).
3 flex_max_i/o_[3] R/W 0 Output signal to MAX PLD (diagnostic use only).
4 flex_diag_3 R/W 0 Firmware controlled diagnostic LED.
5 pit_enable R/W 0 Enable Programmable Interval Timer output pulses.
6 flex_diag_1 R/W 1 Firmware controlled diagnostic LED.
7 /laser_on R/W 1 Patient locator laser control.
Bit Name R/
W
Def. Description
0 low_range_dac R/W 0 Switches mA DAC from 2.048V to 0.500V reference.
1 trans_motor_accel R/W 0 Enables motor interrupt on every micro step.
2 low_range_adc R/W 0 Switches ADC from 5.000V to 0.500V reference.
3 long_motor_accel R/W 0 Enables motor interrupt on every micro step.
4 hvps_vendor_id R N/A For 7681 supply, 0 = Spellman, 1 = Bertan.
5 iq_hvps R N/A Set by resistor placement to indicate 0311/0312 supplies.
6 /hvps_enable_status R N/A Enable status monitor from 7681 supply.
7 /power_up R N/A Set to indicate cold boot.
PORT F
PORT G
2.5.3 TRANS / LONG MOTOR Control and Status
Dual axis stepper motor control is provided entirely by the FLEX PLD. To make a typical move the firmware loads a starting velocity into the 16 bit VELOCITY register, the total number of steps for the move into the 16 bit TARGET register, and step at which to next interrupt the CPU into the 16 bit STEP register. Velocity is in terms of periods of the 2.0MHz fundamental clock per micro step pulse to the stepper drive. The drives provide 10 micro steps per full step. The firmware can track move status by reading the 16 bit READ register.
Bit Name R/
W
Def. Description
0 /motion_fail_enable R/W 1 Arm scanner shutdown if OMI pulses w/o step pulses.
1 long_motor_fail_axis R/W 0 Motor fail circuitry axis control, clear for transverse.
2 /hvps_enable R/W 1 Enable output to 7681 supply.
3 flex_diag_2 R/W 0 Firmware controlled diagnostic LED.
4 /arm_estop_sense R N/A Emergency stop sense bit.
5 spare_jmp_[1] R N/A Unused input, resistor or jumper selectable on CCA.
6 spare_jmp_[0] R N/A Unused input, resistor or jumper selectable on CCA.
7 cpu_p1_2 R N/A Firmware controlled diagnostic LED.
Bit Name R/
W
Def. Description
0 adc_mux_[0] R/W 0 ADC analog MUX input selection control bit.
1 adc_mux_[1] R/W 0 ADC analog MUX input selection control bit.
2 adc_mux_[2] R/W 0 ADC analog MUX input selection control bit.
3 adc_mux_[3] R/W 0 ADC analog MUX input selection control bit.
4 adc_mux_enable R/W 0 ADC MUX output enable control.
5 8ms_clock R/W 0 Clock output provided to MAX PLD.
6 unused N/A N/A For expansion.
7 unused N/A N/A For expansion.
As part of the setup for a move the host and/or firmware must enable the motors via the /motor_power, trans_enable, and long_enable outputs and setup the trans_lsw_override, long_lsw_override, /motion_fail_enable, / motor_fail_enable, and long_motor_fail_axis outputs as desired. If the system is in scanner reset for any reason the FLEX PLD will over-ride the /
motor_power output and prevent 24V power from reaching the motor drives.
Addressing for the motor control interface is provided below.
2.5.4 AGS ROLL
This is a read only 8 bit register which returns the count of AGS roll-over events since the previous read of the register. The AGS roll counter is reset on read only - it is not tied to the PIT's sample clock.
2.5.5 AGS DAC
This port provides R/W access to the AGS circuit's 8 bit U/D counter. The counter is tied via a dedicated 8 bit bus to the AGS DAC. The DAC's analog voltage is tied to the gain control input of the variable gain amplifier (VGA) used to control gain of the detector input signal. As such the firmware can read this counter to determine the current DAC voltage level and hence gain level. If ags_enable is low this port gives the firmware direct control of the AGS DAC as a parallel R/W device. If ags_enable is high, the firmware can write to the port but the DAC will continue to respond to UP/DOWN requests from the AGS DCA circuitry and hence quickly return to the AGS current operating voltage.
HE/LE COUNTERS
These read only ports provide access to the 16 bit event counters which are incremented each time the DCA circuitry detects an input pulse within the HE or LE windows (as defined by the LEL, LEH, HEL, and HEH DAC settings).
These counters are read in two 8 bit bus cycles, MSB then LSB. The event counters themselves consist of a counting element and a bus element. On the rising edge on the PIT output pulse the counting elements are latched to the bus element. The PIT output is also tied to CPU external INT 1 and as such the firmware interrupt handler then has until the next rising PIT edge to read the counters before the bus elements are latched over with the next sample count and data is lost.