Figure 2.13: A standard reconfigurable design with non-relocatable modules. Each region needs its own set of modules.
2.8 Flexible placement and bitstream relocation
A regular reconfigurable design that is created through the Xilinx partial reconfiguration design flow as described in section 2.6 employs location-specific reconfigurable modules. If a design contains several reconfigurable regions, independent instances of a module have to be implemented for each region even if these regions are identical. This is illustrated in figure 2.13. Having to implement separate modules for each region causes an overhead in compilation time and storage size.
A wide range of research considers a more flexible approach where modules are not fixed in their location. One possibility is the concept of fully flexible modules that can be placed anywhere within the free reconfigurable space. This is shown in figure 2.14. As an alternative, designs can have pre-defined reconfigurable regions similar to a non-relocatable design shown in figure 2.13. However, the modules are relocatable between these regions.
This is illustrated in figure 2.15.
Fully flexible placement is often treated as a combined placement and scheduling problem where tasks represented by hardware modules have to be placed within the current free space of the device. For static schedules the placement can be solved offline but for dynamic schedules placement has to be done at run time. In all cases, device fragmentation is an important issue. Kastner et al. present an offline 3D floorplanning technique with time as the third dimension [11]. Reconfigurable modules are treated as cuboids where
2.8. Flexible placement and bitstream relocation 36
Figure 2.14: A reconfigurable design with fully flexible placement of relocatable modules.
configuration repository
Figure 2.15: A reconfigurable design with regions allowing relocation. Modules can be assigned to any region.
the base rectangle represents the module’s dimensions and the height the module’s run time. It is proposed to solve the 3D placement problem with a greedy algorithm or simulated annealing. A run-time version of the problem is also considered, and several algorithms are compared with regard to quality of placement and speed. Diessel et al.
study a two-dimensional dynamic scheduling and placement problem [29]. The analysis is based on rearrangement of modules in order to free up space. Three different compaction methods are compared on an abstract tiled architecture. It is shown that rearrangement can be a viable method to reduce queuing delays. However, the model assumes that tasks can be stopped and restarted at any time without additional overhead. Brebner et al.
consider the problem of flexible module placement in a one-dimensional arrangement [18].
Defragmentation is proposed to reclaim contiguous free space in the device. A concept for communication along the device is also introduced. Kalte et al. create a reconfigurable system with one-dimensional module relocation [51]. This work includes a mechanism that
2.8. Flexible placement and bitstream relocation 37
reconfigurable region 1
reconfigurable region 2
Figure 2.16: Relocation in a heterogeneous device. Reconfigurable regions have an identical footprint.
relocates a module by performing several address translations in the bitstream at run time.
Steiger et al. study several heuristics for one-dimensional and two-dimensional placement and scheduling problems [101]. Tasks cannot be pre-empted because the associated overhead is considered to be unacceptable. Defragmentation is also considered impractical because of the time overhead to unload and reload modules into the FPGA. The heuristics are evaluated in a reconfigurable system consisting of an FPGA managed by a host CPU. The results show that the scheduling time is small compared to the configuration time of a module. Lu et al. introduce a model where placement is not fully flexible [66]. Instead, the FPGA is partitioned in coarse tiles and modules can be placed covering one or several tiles. This reduces the complexity of the placement problem and hence, also reduces scheduling times and rejections caused by fragmentation. All these methods assume a fully homogeneous FPGA architecture without dedicated blocks. This is a precondition for fully flexible placement. Fully flexible placement always suffers from fragmentation issues.
Another important aspect is the inclusion of a communication infrastructure which is often not considered.
Current commercial FPGAs are not homogeneous and contain at least one type of dedicated block. The most common type of dedicated resources are embedded RAMs and these are usually spread throughout the FPGA fabric. Approaches with fully flexible placement assuming a homogeneous FPGA fabric are therefore not applicable for modern FPGAs. Relocation and flexible placement is also possible in heterogeneous devices but the placement options have to be restricted. A simple technique to enable relocation in heterogeneous devices is to identify regions that have an identical footprint, i.e. they provide an identical pattern of resources as shown in figure 2.16.
Horta et al. develop the PARBIT tool that can relocate partial bitstreams within a device or across device types [45]. The tool is used offline and cannot be used for run-time
2.8. Flexible placement and bitstream relocation 38
relocation. The self-reconfigurable platform presented by Blodget et al. also provides routines to relocate a module [14]. Unlike in Horta’s tool, relocation is here performed at run time. Both tools need identical regions as shown in figure 2.16 in order to perform a relocation, but do not consider the problem of how to place a module at run time.
Koester et al. present a module placement technique for heterogeneous architectures [57].
The method finds suitable target regions for a module by identifying identical footprints in the fabric. Two algorithms are presented that aim to optimise the placement based on the probability that tiles will be used by competing modules. This work includes a mechanism for relocating modules by modifying the address fields in the bitstream similar to the one in [51]. Sedcole’s reconfigurable video processing platform is an example of a practical application that uses relocatable modules on a heterogeneous device [93]. Another application is the reconfigurable platform by Hagemeyer et al. [42]. It provides a flexible bus system that allows modules to be relocated and placed anywhere along the bus. In both cases, the system permits flexible 1D placement provided that a suitable identical target region can be found. However, it is not explained how the placement problem is solved.
In a slightly different approach, Koester et al. present a placement technique where the device is pre-partitioned into tiles [56]. Modules can then cover one or several tiles.
The concept is similar to the approach by Lu et al. [66] but also considers heterogeneous devices. Such an approach effectively coarsens the granularity and simplifies the placement problem.
Another possibility is to pre-partition the device into fixed reconfigurable regions as illustrated in figure 2.15. This type of approach has several advantages. It simplifies the placement problem so that modules only have to be allocated to a free region. Furthermore, there are no issues with fragmentation of the device and finally, it is easy to include a communication infrastructure if the possible locations of modules are known at design time.
Sedcole et al. develop such a system with two reconfigurable regions on Virtex-II Pro and Virtex-4 [91]. The regions have an identical footprint and allow relocation. The system presented by Koh et al. has the entire device partitioned into fixed-size reconfigurable regions [58]. The motivation is the simplification of scheduling, placement and the inclusion of communication links. However, relocatability is very limited in this system because of the heterogeneity of the targeted Virtex-4 device: most regions do not have an identical footprint.