FPGA Implementation Results

In this section, hardware implementation results for different VDF designs of the comprehensive ICDM based VDF are presented. To study the trends in resource utilization, power consumption and operating frequency with respect to the prototype filter order, three comprehensive ICDM based VDFs: VDF-I, VDF-II and VDF-III were designed with lowpass prototype filters of orders 60, 120 and 180 respectively. The three VDFs were implemented on a Xilinx Virtex-6 (xc6vlx240t) FPGA based on the hardware implementation architecture shown in Figure 4.6. All the FPGA implementation results presented in this thesis have been obtained using Matlab, Simulink, Xilinx System Generator [95] and Xilinx ISE tools. Digital signal processor (DSP) blocks on FPGAs enable high throughput filter design, however, they are optimized for traditional transposed-form filter structures. High level descriptions can map such transposed-form filter structures efficiently. But while implementing complex and modified filter structures, it is difficult to take advantage of the performance benefits of DSP blocks and hence custom implementations are necessary [96]. Therefore, DSP block inference was disabled for all VDF implementations since the fixed coefficients and the proposed complex modified filter structure do not benefit from their use. Table 4.4 shows the resource utilizations and maximum operating frequencies of the three VDFs, along with

Table 4.4. FPGA implementation results: Comprehensive ICDM based VDF designs.

VDF-I VDF-II VDF-III

No. of occupied slices 4280 7993 12276

Power (mW) 387.07 612.47 1070.74

z-2 Input signal add/ sub mux I 0 1

Decimation Selector (Digital Logic)

h0 M2 z-1 0 1 0 1 0 1 0 1 0 M2 Output 1 sel sel h1 M1 z-1 z-1 _z-1 z-N z-(N-2) z-1 _z-1 m u x II mux I M1 mux I M1 add/ sub z -1 m u x II M2 add/ sub z -1 m u x II sel h(N-1) hN Mout

Figure 4.9. Comprehensive ICDM based VDF: Pipelined hardware implementation architecture.

the corresponding power estimates generated using post-place and route simulation data. In Table 4.4, the number of occupied slices denotes the hardware resource utilization. (Note that in FPGAs, a slice is a hardware resource which contains a set number of look- up tables (LUTs) and flip-flops. For example, in Xilinx Virtex 6 FPGA family, one slice contains four LUTs and eight flip-flops.) Along with the expected increase in resource utilization and power consumption, it is observed that increasing order of the prototype filter results in decrease in the maximum operating frequency. The maximum operating frequency decreases because as the prototype filter order increases, the critical path length increases with depth of the combinatorial computational path. If greater stopband attenuation and narrower transition-band widths are desired in the resultant frequency responses, higher order prototype filters are required which will lead to lower operating frequencies. Therefore, when the frequency response specifications are stringent, the dependence of operating frequency on the prototype filter order will be a major bottleneck if high operating frequencies are also desired. To eliminate this operating frequency bottleneck, a modified hardware implementation architecture for the comprehensive ICDM based VDF is shown in Figure 4.9. The modified architecture is extensively pipelined to break the combinatorial path, which is then balanced in the input data-path by

Table 4.5. FPGA implementation results: Pipelined comprehensive ICDM based VDF designs.

VDF-I-P VDF-II-P VDF-III-P

No. of occupied slices 2985 5789 9188

Power (mW) 190.37 335.35 519.70

Maximum frequency (MHz) 157.853 158.078 157.754

adding delay-chains. The pipelined architecture, though increases the latency from input to output by N clock cycles (for N-order prototype filter), isolates the critical path and prevents the accumulation effect that is present in the original implementation architecture shown in Figure 4.6.

To compare the pipelined architecture (Figure 4.9) with the straightforward non- pipelined implementation (Figure 4.6), the three VDF designs were re-implemented using the pipelined architecture, and the same design options for the same FPGA device. Let the pipelined VDF designs be denoted as VDF-I-P, VDF-II-P and VDF-III-P with prototype filters of orders 60, 120 and 180 respectively. Table 4.5 shows the corresponding implementation results. Comparing the resource utilizations of different VDF designs shown in Tables 4.4 and 4.5, it can be observed that the pipelined designs achieve substantial reduction in the number of occupied slices, despite the increased number of registers used. The pipeline stages added in the designs allow the synthesis tool to optimize the multiplexers and related logic in the delay-chain, thus reducing the overall resource usage. This reduction in resources for the pipelined designs translates to approximately 50% reduction in power consumption, when compared with the non- pipelined implementations. To ensure a fair comparison, all the power estimates were generated based on signal activity rates determined by simulating the designs at an operating frequency of 50 MHz. From Tables 4.4 and 4.5, it can be observed that the pipelined designs achieve much higher operating frequencies than the corresponding non- pipelined designs, and the operating frequencies remain nearly constant across the different VDF configurations with varying prototype filter orders. The average maximum frequency achieved for the pipelined VDF designs was 157.895 MHz. The pipelined implementation architecture shown in Figure 4.9 thus makes the operating frequency of the comprehensive ICDM based VDF independent of the prototype filter order.

4.5 Summary

Based on the ICDM proposed in Chapter 3, different VDF design techniques were proposed in this chapter. An ICDM-I based VDF which provides variable frequency responses by performing the CDM-I and MCDM-I operations was proposed. The ICDM-I based VDF was shown to have greater frequency response flexibility, lower complexity and improved stopband attenuation performance when compared with the conventional CDM-I based VDF. The ICDM-I based VDF can be used in SDR handsets for extraction of individual channels of a single wireless communication standard. An ICDM-II based VDF which provides variable frequency responses by performing the CDM-II and MCDM-II operations was also proposed in this chapter. In the design example considered, the ICDM-II based VDF achieved 57.12% reduction in multiplication complexity when compared with the conventional CDM-II based VDF that was designed for the same frequency response specifications. Also, if the same prototype filter is used, the proposed ICDM-II based VDF offers superior stopband and transition-band characteristics when compared with the CDM-II based VDF. The ICDM-II based VDF can be used for extracting individual channels of multiple wireless communication standards present in the input signal during different time intervals.

A VDF based on the comprehensive ICDM was also proposed. It can perform all the ICDM operations (CDM-I, MCDM-I, CDM-II and MCDM-II) and provides frequency responses with varying subband bandwidths and locations, thus enabling multi-standard channelization. Low complexity FPGA implementations were achieved by pipelining the proposed hardware implementation architecture, which enabled significantly higher operating frequencies that are independent of the prototype filter order. The comprehensive ICDM based VDF can be used for low complexity multi-standard channelization in SDR handsets.

When compared with VDFs based on the conventional CDM, the proposed VDFs offer greater frequency response flexibility and lower implementation complexity. They are therefore compatible for use in SDR handsets, especially in resource constrained battery- operated portable radio handsets. Following the VDFs proposed in this chapter, different filter banks which employ the ICDM technique are presented in the next chapter.

Chapter 5

Design of Uniform and Non-Uniform

Filter Banks using Improved Coefficient

Decimation Method

5.1 Introduction

In software defined radio (SDR) base-station receivers, filter banks that are capable of providing uniform as well as non-uniform subbands are used for multi-standard channelization purposes. Such filter banks can simultaneously extract multiple channels corresponding to different wireless communication standards. It is desired to use filter banks which can provide maximum flexibility in terms of the number, location and bandwidth of the subbands. Also, in applications where the resources available are limited, low complexity filter banks with flexible frequency responses are desired. Three filter banks based on improved coefficient decimation method (ICDM) which can be used for channelization in SDR receivers are presented in this chapter. The subsequent sections present the proposed filter banks in detail along with their generalized design procedures, design examples and comparison with other relevant filter banks in literature. The ICDM- I based filter bank, ICDM-II based filter bank and the comprehensive ICDM based filter

bank described in Sections 5.2, 5.3 and 5.4 of this chapter have been published in [J1, C3], [J2] and [J3] respectively.