Fractional-N Single Loop Frequency Synthesisers

Within a frequency synthesiser that uses a digital divider in the feedback path, the n- division value raises the level of in-band phase noise by raising the loop gain response to the reference input signal and phase detector noises. To overcome this problem the concept of reducing the feedback n-division value, and hence raising the sampling frequency found at the PFD input has led to the evolution of fractional-n synthesisers.

This has led most manufacturers to produce a fractional-n device, each with their own technique that allows integer dividers to be used in a pseudo fractional manner, whilst simultaneously maintaining the spurious performance expected of an integer-n synthesiser. Inevitably there is a penalty for modulating the integer n-dividers to give a mean fractional value, and this has resulted in a variety of patents being generated each aiming to reduce these spurious products. Figure 2.2.

The recent commercial interest in fractional-n frequency synthesisers has been based upon their perceived ability to optimise the performance of a frequency synthesiser by increasing the PFD sampling Frequency. With an increased PFD sampling frequency an expected decrease of in-band noise is anticipated allowing the loop bandwidth to increase. Hence the combination of improved in-band noise performance and increased loop bandwidth should theoretically make fractional-n frequency synthesisers suitable for meeting the specifications of a variety of otherwise impossible applications. However, it is worth considering the practical limitations of fractional-n frequency synthesis. - 5 0 -r -60 ■ — - 7 0 --- Fractional-n, /,= 10M H z /„ = 255.8MHz 1 -80 ■ - m 2 . -90 ■ |i u -100 - 3 -110' % azQ. g 03 -130 - ÙO -140 ■ Integer-n, / , =10MHz /„ = 250MHz 150 -160 100 Ik H z lO k H z lOOkHz I M H z lO M H z lO O M H z Frequency O ffset, ( Hz )

Figure 3.3 Comparison between fractional and integer-n SSB phase noise performance Reviewing all the data sheets offered by manufacturers of commercial fractional-n synthesisers, it soon becomes clear the anticipated in-band phase noise expected with

the higher PFD sampling frequencies, is not actually achieved. With the exception of Fan, [48], no explanation for this observed degradation has been offered.

Figure 3.3 is the measured SSB phase noise performance taken from a simple experiment that used the same synthesiser digital dividers and PFD driven firstly in integer-n mode and then by a simple first-order sigma delta fractional-n PLL^. From Figure 3.3, it is clear that the in-band phase noise performance is degraded by 3dB, whilst those parts of the SSB phase noise profile attributable to the VCO remain unchanged. This result suggests the in-band phase noise performance does not improve as much as expected, preventing the loop bandwidth from being increased to the desired extent. Furthermore, with only a modest increase in loop bandwidth and a reduction in the “V” feedback fraction used in the loop filter component calculations, the loop filter components quickly become very large in value, especially the capacitors. Figure 3.4.

C harge Pum p C urrent V C O Tune V oltage /?, V alues C, V alues /?, V alues C, V alues Cj V alues 10 10 L og N D ivision V alue 10

g

I

Figure 3.4 Loop filter values for increasing n-division values.

F o r the p u rp o s e s o f th is e x p e rim e n t no a tte m p t w as m ad e to c o m p e n s a te fo r th e larg e sp u rs, by m o d ify in g th e lo o p filter in e ith e r m easu rem en t.

The problem with larger capacitor values is the dielectrics used have increased leakage, which as shown in section 3.4.2, will extend the lock time. In an attempt to reduce the size of these loop filter capacitor values the temptation is to reduce the loop gain. Assuming the n-divider value remains the same, then potentially only the charge pump gain, or the VCO gain can be reduced. Adjusting the VCO gain is not normally possible because of the tuning range versus available tuning voltage constraint, which leaves only the charge pump gain. Decreasing the charge pump gain, (or PLL error signal), is not normally the preferred solution in any closed loop system, particularly in low noise applications, because it requires the real resistive part of the loop filter to increase. Figure 3.5, to compensate for the change in loop gain. This increase in the resistive component of the loop filter raises the loop filter thermal noise contribution to the overall PLL noise. Therefore in a practical fractional-n synthesiser application a compromise between the charge pump gain and the maximum sampling frequency, which scales the loop filter component values, has to be made.

600 140 C harge P um p C urrent 120 VC O Tune Voltage 500 100 "ST 400 80 .2 300- > Û! 200- • 1 0 0- • - 20 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 18 2 2.2 2.4 2.6 2 8 3 3.2 3.4 3.6 3.8 4

Charge Pump Current, {mA}

Figure 3.5 Tvpical variation of loop filter values for increasing charge pump gain In conclusion, some of the potential advantages of a fractional-n synthesiser are lost with its disappointing in-band phase noise performance and the limitations of the large capacitors necessary to build the loop filter. For this reason, fractional-n frequency

synthesiser techniques were dismissed in this study, as the single solution capable of meeting the demands required for a frequency agile, low noise synthesiser.