Front End Electronics and Data Acquisition

The front end readout electronics has to fulfill several requirements to achieve the envisaged performance of the PANDA EMC. The energy range from the low single crystal threshold of 1 MeV up to the maximum expected energy deposition in a sin- gle crystal of 12 GeV has to be covered resulting in a dynamic range of 12, 000. In addition, the limited space within the EMC cooling compartment should be used effi- ciently. On that account, the preamplifier should be as close as possible to the crystal sensors which features a decreasing probability of pick up noise. Furthermore, a low power consumption of the preamplifiers is essential to guarantee a homogenous cooling along the crystal. Two different concepts were developed for the two envis- aged photo sensors. On the one hand the ASIC for PANDA Front-end ELectronics (APFEL) Application Specific Integrated Circuit (ASIC) was developed as a pream- plifier for the Barrel part and on the other hand the Low Noise and Low Power charge Preamplifier (LNP-P) for the FEC. Both concepts will be described in the following

sections.

1.3.8.1 ASIC

Each crystal within the Barrel EMC is equipped with two LAAPDs which are read out simultaneously by one ASIC, the so-called APFEL [34]. An APFEL ASIC has two equivalent channels per chip. Each readout channel consists of a charge sensi- tive preamplifier, a third order semi-Gaussian shaper stage and a differential output driver. The schematic layout of this kind of ASIC is displayed in Fig. 1.27 and a picture can be seen in Fig. 1.28. Preamplifier and shaper use state of the art 350 nm

Figure 1.27: Schematic layout of the APFEL. Marked are the charge sensitive pream- plfier (red), the third order shaper stage (green) and the differential out- put driver (blue).

Complementary Metal-Oxide-Semiconductor (CMOS) technology operated at 3.3 V single core voltage. The complete readout electronics fit on 3.4 × 3.5 mm2. The in- put of one LAAPD is split by the APFEL which provides two outputs with different amplifications to cover the dynamic range. Their relative gain can be programmed to a factor of 16 or 32. The design features to be more sensitive to low energies in the high gain branch while it is still possible to observe the complete energy range with the low gain branch. A maximum input charge of 8 pC results in a digital dynamic range of > 10, 000. At GSI an Equivalent Noise Charge (ENC) of (4125 ± 67) e− was measured at T = −25◦C while 4500 e−were required. Furthermore, the APFEL is able to handle the required event rates of 350 kHz and the power consumption is less than the required 60 mW per ASIC. The digital part of the APFEL features a serial interface on the chip for autocalibration to detect the right DC voltages for a given temperature. The output DC voltage is dependent on the temperature result- ing in a change of operating points of the amplifier. The dependency was measured and amounts to 25 mV/K. Hence, with fixed voltage references a temperature shift would lead to a decreasing dynamic range of 2%/K. This is solved with an adjustable voltage reference. In addition, an optional charge injection as a test pulser is possible, the DAC setting can be read and written and each chip has an ID for single chip and bus communication.

1.3.8.2 Low Noise and Low Power Charge Preamplifier

The photo sensors in the FEC, both LAAPDs and VPTTs, will be read out with variations of the LNP-P developed at Basel University [35]. Here, there is only one preamplifier channel per photo sensor. Further, an additional shaper board is needed to guarantee high rate capability together with the currently developed Sampling Ana- logue to Digital Converter (SADC). A former version of this preamplifier is used in the Barrel EMC prototype PROTO60. A LNP-P is based on Junction Field Effect Transistor (J-FET) technology where the input charge is linearly converted into a positive output voltage. The power consumption of a single LNP-P is in the range of 45 mW up to 90 mW depending on the event rate and energy of the photons.

Figure 1.28: Picture of the APFEL 1.4 ASIC.

1.3.8.3 Data Acquisition

The schematic layout of the PANDA EMC DAQ is depicted in Fig 1.29. The pre- amplified and shaped signals from the photo sensors are routed from the cold volume to a digitizer module for digitization. The digitizer module consists of an SADC and an on-board Field Programmable Gate Array (FPGA) for feature extraction and hit building. The online pulse data processing is performed in two stages. First, pulses are identified by monitoring the continuously digitized signal baseline. In case of a pulse, a time stamp is set to the maximum. Additionally, possible pile-up is indicated. In the second stage, the precise time and pulse height are determined. This hit data is then transmitted via optical links to the data concentrator. The task of the data concentrator is the EMC event building which includes time ordering, pile-up recovery and synchronization and communication of the SADC clock information with the global time distribution system and slow control information. A processed event is then send to the compute node. Here, the information of the other sub- detector systems is connected with the EMC information and the online physics event reconstruction takes place. Flexible software trigger conditions are set to store events to hard disk. The conditions are not tuned to specific reaction channels like for most

Figure 1.29: Schematic layout of the PANDA EMC DAQ [27].

hardware triggers. Thus, most channels and possible rare reactions are not suppressed at PANDA. The amount of collected data is only limited by the dead time of the individual sub-detector systems and the buffer size of the compute node.

Beamtime test with PROTO60

2.1 PROTO60

The PROTO60 is the first real-size prototype of the PANDA Barrel EMC. The geom- etry is arranged to resemble a subsection of a barrel slice, as schematically shown in Fig. 2.1. It consists of 60 geometry type-6 L & R shaped PWO-II crystals arranged in 10 columns and 6 rows. The difference to a barrel slice is that only maximum 4 rows of the same type are grouped together. The reason is a simplification of the carbon alveoli holding structure in case of the PROTO60. In addition, a crystal is read out with only one LAAPD. As in the Barrel the crystals are operated at a temperature of −25◦_{C. Mechanics, electronics, readout and DAQ of the PROTO60 are described in}

the following sections in more detail.