Functional Verification

4.2.1 Basic MIPS Verification

Functional verifications began with the lowest levels of the Basic MIPS architec- ture and worked their way to the highest level modules. All functional verifications were conducted using Mentor Graphics QuestaSim software. The VHDL code for components and subcomponents of Basic MIPS along with testbench VHDL files to stimulate the inputs of the various components and subcomponents were compiled by and simulated in QuestaSim. Low level verifications were conducted on the NAND gate and D-flip-flop. These low level verifications were full factorial verifications; ev- ery possible input combination was attempted. Every NAND gate input combination (00, 01, 10, and 11) were attempted to verify the correct output (1, 1, 1, 0). The D-flip-flop was tested to ensure that every successive input was stored, whether the input order was 00, 01, 10, or 11. Full factorial verifications were conducted for all low level modules where the total number of input bits was fewer than nine (i.e. a 4-bit adder with two 4-bit inputs and one 1-bit input).

For higher level modules, full factorial tests were not conducted because there is insufficient time to conduct such tests. Instead, test patterns were loaded and results checked to ensure simulation results matched expected results for each test pattern (i.e. 32-bit adders, 32-bit shift operations, 32-bit AND, ALU, GPRs, and etc.). It was assumed that full factorial verifications of lower level modules when combined with test patterns for higher level modules was sufficient to verify correct operation of the higher level modules. For the Datapath module level, there are far too many inputs which must be synchronized to correctly verify its function; therefore, the Datapath functional verification was done in conjunction with overall Basic MIPS functional verification. Basic MIPS functional verification combined the Datapath

verification and correctly articulates all of the Datapath’s inputs, the Datapath’s functional verification can be conducted in conjunction with Basic MIPS functional verification.

The Controller functional verification consisted of supplying the Controller with valid instructions when the Controller attempted to read an instruction from mem- ory. Each of the 33 Basic MIPS instructions were verified. Branch instructions were verified to ensure that they worked correctly whether the branch should be taken or not taken. These inputs were much more manageable than the Datapath inputs. Ad- ditionally, erroneous instructions were also provided to ensure the Controller rejected such instructions and attempted to re-read the instructions from memory.

After Controller verification, the Datapath was connected to the Controller to form Basic MIPS. The same inputs that were supplied to the Controller for verification were supplied to Basic MIPS for verification. These verification tests uncovered some problems with the Datapath, the Controller, and the interface between the two. These problems were corrected, then Basic MIPS passed functional verification.

Functional verifications were also performed on the Memulator to ensure that it correctly performed read and write operations. These operations consisted of reading and writing patterns to a number of different memory addresses; however, these operations were not a full factorial test to test reading and writing to every possible 32-bit word to every possible 32-bit address. These operations were sufficient to provide Memulator verification.

Finally, the Memulator was combined with the Basic MIPS processor to ensure correct operation. The only inputs supplied by the testbench VHDL code were the master clock and master reset signals used by both Basic MIPS and the Memulator. Some errors were identified and corrected at this stage as well. After fixing these errors, the Basic MIPS processor was able to successfully read instructions from

memory and process them correctly. The processor was also able to successfully write to memory. The Memulator successfully reset itself and the processor upon program completion. To test program completion, the number of loops was reduced to three because the software simulation cannot handle doing 999 loops due to resource limitations of the computer running the software simulation.

4.2.2 TMR MIPS Functional Verification

TMR MIPS verification uncovered a couple of problems with Basic MIPS that were previously unidentified. These Basic MIPS problems were corrected and Basic MIPS was re-verified before resuming TMR MIPS verification.

The TMR Voter was verified as integrated into TMR MIPS rather than being verified independently due to its complexity. TMR MIPS was verified by allowing TMR MIPS to attempt to run Basic MIPS programs in a software simulation. These simulations enabled verification of correct TMR Voter state transitions during error free operations. Save/restore point creation was also verified. These simulations also ensured that TMR MIPS would reset correctly upon receiving a DONE signal from the Memulator at program completion. Some errors in TMR MIPS were uncovered and corrected as a result of the verification tests.

4.2.3 TSR MIPS Functional Verification

TSR MIPS functional verification revealed that some branch instructions used only by TSR MIPS programs were not being processed correctly by Basic MIPS. Basic MIPS branch processing was corrected, then Basic MIPS and TMR MIPS were re-verified before resuming TSR MIPS verification. After these corrections, TSR MIPS programs successfully executed on the Basic MIPS processor in software simulations. TSR MIPS save/restore point creation instructions were also verified.

The simulations also confirmed that TSR MIPS was correctly reset by the Memulator upon program completion. TSR MIPS error recovery instructions were verified once errors were injected into TSR MIPS.

4.2.4 AHR MIPS Functional Verification

AHR MIPS functional verification began with ensuring AHR MIPS allowed TMR MIPS to operate correctly since AHR MIPS begins in TMR mode after starting the processor. The next step was to verify the TMR to TSR transition in an error free software simulation. The TMR to TSR transition was also verified after some minor problems with the AHR Controller FSM were discovered and corrected. All regis- ters and memory locations were correctly updated as the AHR Controller correctly transitioned between states. No additional problems were discovered in Basic MIPS, TMR MIPS, or TSR MIPS during these verification tests. The verification tests were also able to evaluate the TSR to TMR transition by using error injection.