Chapter 6 Conclusions and Future Work
6.2 Future Work
The 1D clustering circuit is shown in figure 1.6. Graphene transistor will be
biased by current provided by current mirror embedded in CMOS chip. Figure 6.1 shows working area on the chip and explains the function of each pad. Graphene channel will be in pad in2. Drain will be at p drain and source will be at N drain pad. N drain is the drain pad of an Nmos transistor. It will be connected to be graphene source and shorted with Vss.
Figure 6.1. Working area of 1D clustering circuit on the CMOS chip.
High modulation ratio, low hysteresis and symmetric transfer curve has been achieved for graphene FETs on flat SiO2 substrate. However, the surface of aluminum pad in CMOS chip has roughness up to 80 nm as shown in figure 6.2
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Figure 6.2 AFM image of aluminum pad (left) and line profile taken along the white line in AFM image (right).
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which is detrimental to deposited dielectric integrity. Aluminum pads are 4 um lower than the outside polyamide surface causing difficulty in graphene film landing on the pad. The graphene FET has been fabricated within pad in2 as shown in figure 6.3. 7.6 nm SiO2/16.8 nm Al2O3 was deposited on chip by ALD.
The oxide at the right down corner was etched and aluminum was deposited for extending the gate pad to the big electrode out of the pad. Fine source or drain electrodes were patterned by EBL and then connected to bigger electrodes out of the pad. At this stage, the graphene FET was biased by external voltage source.
Transfer curve shows no hysteresis and low modulation. When further increasing gate voltage, the oxide got broken down at the voltage much lower than the supposed breakdown voltage for 7.6 nm SiO2/16.8 nm Al2O3.
Figure 6.3. SEM image of a graphene FET fabricate on the chip pad (left) and transfer curve of the graphene FET (right).
Further work needs to be done with achieving good dielectric integrity. Metal lift-off on rough chip surface is always hard and the reason is unknown. Graphene is
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vulnerable to the fierce metal lift-off. So the whole fabrication process still needs to be optimized to increase the success rate. In future the device needs to be biased by the internal current source.
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Vita
Wan Deng was born in Songzi, a small city in the southwest of Hubei Province in China. Wan Deng got her B.S. degree in Electronic Science and Technology from Shaanxi University of Science and Technology in July 2010.
Wan Deng is currently pursuing her Ph.D. degree in Dr. Gong Gu’s group in the Department of Electrical Engineering and Computer Science, the University of Tennessee at Knoxville. Her research interests include application of two dimensional materials in novel electronic and optoelectronic devices.