Functional Verification
6.2 Future Work
The present project had as one of its main ideals, the purpose of allowing further scaling. It was thought and designed having in mind future improvements and upgrades. This was a scalable prototype, aimed to study and find a solution to interface between video transport platforms. Some of the proposed future work is product of resource constraints, other is product of previously thought upgrades and possible additions.
• Improvement of validation tools. The validation system consists of a video generation block responsible to generating stimulus in the project inputs. However, as already explained, the ancillary data, despite being in conformity with the standards, is not valid, or in other words, is dummy. That means it cannot be validated in all its extension. For example, the timecode values are not generated, which means that a 4 cable system, which is completely dependent of order synchronization of video data could not be constructed before correct timecode generation.
• Scale the network protocol. SMPTE 2022-6 is only standardized for 3G video over IP, however, in conjunction with the 10Gb Ethernet solution, it would be possible to manage multiple SMPTE 2022-6 implementations in parallel, generating parallel datagrams, so that better video formats could be transported in the network.
• 4 cables system. As mentioned during the Requirements analysis, this system is the fun-damental pillar of a 4 cable system targeted to transport 4K video as 4 1080p frames as defined on the SMPTE 425-5 standard (figure6.1). This would be the next obvious stage in terms of performance upgrades. 4 SMPTE UHD-SDI modules would be required, each of which would be in charge of dealing with one 1080p video resolution. Timecodes would be a critical feature, as well as memory accesses.
6.2 Future Work 73
Figure 6.1: The 425-3 and 425-5 SMPTE standards to define 4K frame using four sub-images [41]
Figure 6.1 shows how SMPTE 425-3 and SMPTE 425-5 standardizes the transport of 4K frames on 4 streams.
• Improving the system to 4K using the 12-SDI. This would be the natural improvement if 8K is an objective. It would also be possible to use 16 3G-SDI cables for an 8K system, but that would be more resource demanding. Moreover, the hardware would become far more complex and expensive and the logic organization also prone to fails. Improving the system to 12G-SDI would require the usage of 2 different clock sources, due to Clock Recovery Unit demands. The QPLL would also need to be used, and the clock frequency used would be 297MHz. This would demand stricter timing requirements. In spite of the high demands, the developed system is ready to be upgraded this way. The upper wrapper allows for easy changing of CPLL, QPLL and SMPTE UHD-SDI parameters in order to perform the upgrade. The SMPTE UHD-SDI module would use 16 video streams instead of the 2 used on the actual system. Despite the changing in configurations, timecodes would again not be a critical step, since the whole video information would be transmitted through 1 single cable.
• Implementing 8K system. If the 4K system using 1 cable on the 12G-SDI mode mentioned above, was implemented, then an 8K system would be a possible step further. This solution is not standardized and is still only target of prototyping. However, it would be at the moment the most resource balanced way of achieving 8K resolutions.
• Implementing the Internet layers. As a result of resource constrains the implementation of a real IP system output and its layers was not implemented. Therefore, the step to transform this prototype into a real product would be to implement the remaining system. A valid 10
Gb Ethernet solution was already analyzed and could be the base of a more complex internet distribution dedicated system.
• Forward Error Correction (FEC). The developed system incorporates CRC techniques that allow the SMPTE UHD-SDI Receiver to identify if there were video transmission errors during SDI transmission. However, the change of platforms from SDI to IP brings out a different kind of data losses. Despite network packet loss, which is properly identified by the RTP protocol, packet corruption can also be a problem. Therefore, the Forward Error Correction algorithm can be applied to endure video network packets reliability. It is also described on the SMPTE 2022-6 standard.
• Dynamic Partial Reconfiguration. The next step related to dynamic partial reconfiguration is to implement an automatic system capable of loading the bitstreams when an event is triggered.
References
[1] Jeremy G. Butler. Television: Critical Methods and Applications. Taylor & Francis, 2006, 2006.
[2] Consumer Electronics Association (CEA). The Future is Clear – 4K Ultra High-Definition Continues to Build Positive Momentum, January 2015.
[3] Adam Flomenbaum. New research highlights rapid growth of 4k TV sales, cord-cutting households, 2015. [Online; accessed June
24, 2016]. URL: http://www.thedrum.com/news/2015/10/15/
new-research-highlights-rapid-growth-4k-tv-sales-cord-cutting-households. [4] Charles Poynton. Digital Video and HDTV Algorithms and Interfaces. Number
1-55860-792-7. Morgan Kaufmann Publishers, 2003.
[5] John Hudson and Nigel Seth-Smith. 3G – The evolution of the Serial Digital Interface (SDI), January 2006.
[6] ADT Security Systems. Networked Video (Video Over IP) Benefits: A Guide for Small- to Medium-Sized Businesses. Technical report, ADT Security Systems, 2009.
[7] EBU UER. Advice on the use of 3 Gbit/s HD-SDI interfaces. (Technical Report 002), July 2011.
[8] Richard F. Zarr. 4K Video: The Next Revolution. June 2014. [Online;
accessed June 24, 2016]. URL: http://electronicdesign.com/embedded/
4k-video-next-revolution.
[9] Xilinx. Video over IP. [Online; accessed June 24, 2016]. URL:http://www.xilinx.
com/applications/broadcast/video-over-ip.html.
[10] Jeawoo Kim Hyun, Sangjin. Implementation of real time 4K S3D/8K UHD Capture system.
[11] M. Mitchell Waldrop. The chips are down for Moore’s law, February 2016.
[Online; accessed June 24, 2016]. URL: http://www.nature.com/news/
the-chips-are-down-for-moore-s-law-1.19338.
[12] Ilkka Tuomi. The Lives and Death of Moore’s Law. (Volume 7, Number 11), Novem-ber 2002. [Online; accessed June 24, 2016]. URL: http://firstmonday.org/ojs/
index.php/fm/article/view/1000/921.
[13] Farzin Piltan. Research of Full Digital Control for Nonlinear Systems (e.g., Industrial Robot Manipulator, IC Engine, Continuum Robot, and Spherical Motor) for Experimental Research and Education Investor. Technical report, Iranian Institute of advanced science and Technol-ogy (IRAN SSP), 2012.
75
[14] Louis Frenzel. Handbook of Serial Communications Interfaces: A Comprehensive Com-pendium of Serial Digital Input/Output (I/O) Standards. Newnes, 2015.
[15] SMPTE. Payload Identification Codes for Serial Digital Interfaces. (SMPTE ST 352-2010), March 2011.
[16] Wikipedia, the free encyclopedia. 8K UHD, 4K SHD, FHD and SD, 2015. [Online; accessed June 24, 2016]. URL: https://commons.wikimedia.org/wiki/File:8K,_4K, _2K,_UHD,_HD.png.
[17] Chroma subsampling, 2015. [Online; accessed June 24,
2016]. URL: http://calendar.perfplanet.com/2015/
why-arent-your-images-using-chroma-subsampling/.
[18] Charles S. Swartz. Understanding Digital Cinema: A Professional Handbook. Taylor &
Francis, 2004.
[19] Makarand Tapaswi. Why the RGB to YCbCr, July 2009. [Online; accessed June 24, 2016]. URL: https://makarandtapaswi.wordpress.com/2009/07/20/
why-the-rgb-to-ycbcr/.
[20] SMPTE. UHDTV Ecosystem Study Group Report. March 2014.
[21] SMPTE. 3 Gb/s Signal/Data Serial Interface. (SMPTE 424M-2006), April 2006.
[22] Tektronix. Broadcast Data Analysis. 2011.
[23] Xilinx. Zynq-7000 AP SoC and 7 Series Devices Memory Interface Solutions v2.4. Techni-cal Report WP-01055-1.0, Xilinx, March 2008.
[24] DDR comparison, 2004. [Online; accessed June 24, 2016]. URL: http://www.
xbitlabs.com/articles/memory/display/ddr2_4.html. [25] Xilinx. SMPTE UHD-SDI v1.0. (PG205), April 2015.
[26] Young Engineering. A-Law/Mu-Law Companding. (Revision 1.0), May 2003.
[27] Ralf Neuhaus. A Beginner’s Guide to Ethernet 802.3. (EE-269), June 2005.
[28] Industrial Ethernet Book. 10GbE relationship to OSI layer model, 2016. [Online; ac-cessed June 24, 2016]. URL: http://www.iebmedia.com/ethernet.php?id=
5488&parentid=74&themeid=255&hft=39&showdetail=true&bb=1. [29] Xilinx. XAUI v12.1. (PG053), November 2014.
[30] Agilent Technologies. 10 Gigabit Ethernet and the XAUI interface. Technical report, Agilent Technologies, 2002.
[31] Marco D. Santambrogio et al Hsiung, Pao-Ann. Reconfigurable System Design and Verifica-tion. Number 9781420062670. Springer Science & Business Media, 2010.
[32] Video resolutions, 2014. [Online; accessed June 24, 2016]. URL: https://www.
todoespacoonline.com/post.php?id=2745.
REFERENCES 77
[33] Xilinx. Xilinx Virtex-7 FPGA VC7203 Characterization Kit, 2014. [Online; accessed June 24, 2016]. URL: http://www.xilinx.com/products/boards-and-kits/
ck-v7-vc7203-g.html.
[34] Xilinx. Zynq-7000 AP SoC and 7 Series Devices Memory Interface Solutions v4.0.
(UG586), June 2016.
[35] SMPTE. SMPTE Standards Update Webcast: Video Over IP Using The SMPTE 2022 Stan-dards, June 2013. [Online; accessed June 24, 2016]. URL: https://www.youtube.
com/watch?v=ZtQdAvwSe1E.
[36] SMPTE. Transport of High Bit Rate Media Signals over IP Networks (HBRMT). (SMPTE ST 2022-6:2012), October 2012.
[37] Xilinx. Implementing SMPTE SDI Interfaces with 7 Series GTX Transceivers. (XAP1249 (v1.1), August 2015.
[38] Xilinx. Virtex-7 FPGA VC7203 Characterization Kit IBERT. (UG847 (v8.0)), October 2014.
[39] Xilinx. VC7203 Virtex-7 FPGA GTX Transceiver Characterization Board. (UG957 (v1.3)), October 2014.
[40] Xilinx. Partial Reconfiguration. (UG947 (v2014.3)), October 2014.
[41] SMPTE. SMPTE 425-3 & SMPTE 425-5, June 2014. [Online; accessed June 24, 2016]. URL: http://www.deltacast.tv/news/news/2014/
deltacast-early-adopts-smpte-425-3-and-smpte-425-5-standards-for-4k-video.