Figure 4.18: UART Baudrate generator.
4.3.3 Transmitter and transmitter FIFO modules
The transmit FIFO (TxFIFO) stores the data from the AXI TxFIFO register, up to eight bits upon a write transaction. When data is written, the empty flag
is cleared, remaining low until all the data is removed and sent by the transmit-ter. This FIFO provides event and interrupt flags such as, TxFIFO full interrupt status (TFULL), TxFIFO nearly-full flag (TNFULL), threshold trigger (TTRIG), that indicate if the FIFO is full, nearly full (one more write left), or reached the programmed fill level, respectively.
The Transmitter gets the data from the TxFIFO and serializes it, Figure 4.19 illustrates this module state machine. Firstly, the TxFIFO level is verified, and if it is not empty a read enable to the TxFIFO is issued and the start bit is sent.
If the data was successfully read from the FIFO (TxFIFO valid signal high) the data bit transmission is started, otherwise the transmission is restarted. Once in the data bits transmission state, the character is serialized and each data bit is sent one by one at the corresponding baud rate. Also, high level data bits are accounted in order to send the parity bit afterwards, if enabled at the device’s configurations. When the number of sent data bits reaches the value configured at the mode register, the transmitter state is updated. If the parity bit is enabled at the mode register, the parity of the sent data bit is verified and sent accordingly high/low, for one baud rate clock, otherwise this last step is disregarded. Then, for the stop bit state, the number of configured stop bits at the mode register is transmitted, also at the baud rate.
Counter = bit nbr
&
No parity bit IDLE
DATA_BIT
PAR_BIT START_BIT
(TxFIFO WR_enable)
BREAK STOP_BIT
Stop Transmission Break
TxFIFO Valid write
No Transmission Break START
START
Figure 4.19: Transmitter finite state machine.
Lastly, before returning to idle state and ready to transmit other data, the transmitter checks if a transmission break was issued, and in such case, the trans-mitter will be locked in a "break" state until a stop transmission break is issued, thereupon returning to the idle state and ready for the next transmission. Other-wise, without receiving any transmitter break the transmitter returns directly to the idle state after the sending the stop bits. Throughout the various transmitter states, the Tx signal is set accordingly to the current state, parity configuration, and current data bit (if in data bit state), as shown in Listing 4.4.
1 a s s i g n Tx =
2 ( s t a t e == I D L E ) ? 1 ’b1 :
3 ( s t a t e == S T A R T _ B I T ) ? 1 ’b0 :
4 ( s t a t e == P A R _ B I T && m r _ p a r [0] == 0 && m r _ p a r [1] == 0) ?
5 ( n b r _ o f _ o n e s _ r e g % 2 == 0) :
6 ( s t a t e == P A R _ B I T && m r _ p a r [0] && m r _ p a r [1] == 0) ?
7 ( n b r _ o f _ o n e s _ r e g % 2 != 0) :
8 ( s t a t e == P A R _ B I T && m r _ p a r [0] == 0 && m r _ p a r [ 1 ] ) ? 0 :
9 ( s t a t e == P A R _ B I T && m r _ p a r [0] && m r _ p a r [ 1 ] ) ? 1 :
10 ( s t a t e == S T O P _ B I T ) ? 1 ’b1 :
11 ( s t a t e == B R E A K ) ? 1 ’b0 :
12 ( s t a t e == D A T A _ B I T ) ? d a t a _ r e g [ g l o b a l _ c o u n t e r ] : 1 ’b0 ;
Listing 4.4: Tx signal set according to current state. Verilog code extract.
Figure 4.20 illustrates a complete transmitted data stream synchronized with the respective baud rate, and configured with a eight data bit length, parity bit and one stop bit.
Figure 4.20: Transmitter data stream.
4.3.4 Receiver and receiver FIFO modules
The receiver FIFO (RxFIFO) stores data up to eight bits, from the receiver mode. This FIFO provides event and interrupt flags such as, RxFIFO full interrupt status (RFULL) and the threshold trigger (RTTRIG) that indicate if the FIFO is full or reached the programmed fill level, respectively.
Counter = char number & No parity bit
IDLE
CHAR_LENGTH
WAIT FIFO LAST
THREE SAMPLES
DONE (RxFIFO write
enable)
STOP_BIT START
START
Character stored
PAR_BIT
Counter < stop bit nbr
Figure 4.21: Receiver finite state machine.
The receiver module is responsible for continuously over-sampling the RxD signal, gathering the data which is being serialized, and storing the received UART data. This state machine is illustrated in Figure 4.21. When a sample detects the RxD transition to low level it waits for half of the configured baud rate divider value, collects three more samples and verifies if the RxD signal remained low.
If the signal remained low until this point, the receiver considers it as a valid start bit, otherwise, the same process is performed in the next RxD negative edge.
Upon a valid start bit detection, the receiver baud rate clock is resynchronized in order to collect three samples around the data bit mid-point, as shown in Figure 4.22.
Baud sample RxD Rx Baud rate
Data bit
Last 3 sample s de termi ne the data bit Figure 4.22: Resynchronized baud rate at data bit mid-point.
When the resynchronized baud rate is high, the last three samples are collected and the selected data bit is determined by majority voting, and the number of high level selected bits is recorded for parity checking purposes. The former process is repeated at a specific baud rate, until the number of selected bits meets the number of characters configured in the mode register. Then, the receiver enters the stop bit state, receiving the number of expected stop bits, also configured in the mode register. After receiving the stop bits, if the RxFIFO has space for the received data, the write enable signal is activated and the data stored in the FIFO. Otherwise, if the FIFO is full, the receiver waits for available space to store the data in the FIFO. However, if a new valid start bit arises when the receiver is waiting for FIFO space, the assembled character is dumped and the overflow interrupt issued.
In addition to the overflow interrupt, the receiver module also generates other already mentioned interrupts, such as: parity interrupt, when the parity of the received data bits is calculated, in accordance with the respective mode register bit field, and does not match the received parity bit; framing interrupt, when the received number of stop bits counter doesn’t match the expected number (configured on mode register); and the timeout interrupt, when a global counter that keeps track of the amount of time since the receiver is in idle state waiting for a valid start bit exceeds the programmed value, configured in the respective AXI register.
4.3.5 Mode switch module
The mode switch module uses the mode register configuration bit to control the RxD and TxD signals routing. This module enables the UART to operate in several modes show in Figure 4.23, such as: (i) normal mode, the standard for UART operations, where the receiver and Rx and Tx signals pass-through the mode switch module, directly to the respective RxD and TxD pins; (ii) automatic echo mode, where the received data from the RxD pin is routed to both the re-ceiver module and the TxD Pin, immediately transmitting what is being received and stored; (iii) local loopback mode, where both the RxD or TxD pins are un-connected, instead the transmitter Tx output signal is directly connected to the receiver Rx signal (normally used for test purposes); (iv) remote loopback mode, where the RxD and TxD pins are connected to each other and the UART cannot transmit or receive any data, consequently received data is directly transmitted back.
Mode
Figure 4.23: UART operation modes.
4.3.6 Modem control module
The modem control module is used to manage communication between the UART and a modem. The module has two associated registers, illustrated in Figure 4.24: The modem status register, contains the current status of Delta Clear to Send, Delta Data Set Ready, Trailing-edge Rind indicator and Delta data carrier detect. Whenever one of these modem signals status changes, an interrupt is issued, by setting the interrupt status bit at the DMSI bit in the interrupt status register. The modem control register sets the data terminal ready (DTR) and request to send signals, and is able to configure the flow control mode as either automatic or Manual. The flow control mode is by default manual, hence the request to send (RTS), and data terminal ready (DTR) are completely controlled by the modem control register. However, if the flow control mode is configured as automatic, these signals are asserted and de-asserted based on the current FIFO level and configured flow delay register, and transmission in only possible when the clear to send signal is asserted.
... 1 0
Figure 4.24: UART modem registers layout.