Impacts of Clock Jitter

When a clock experiences jitter, it affects the performance of the device or system that uses it. We will discuss the impact of clock jitter on two distinct link systems: synchronized and asynchronized.

7.1.2.1. Synchronized System

A synchronized system is commonly used in computer applications. Figure 7.2 shows a typical synchronized link system in which a global clock is used to update and determine the logical bits for driver, sampler, or register.^[4], ^[5] If the clock has jitter, it degrades the systems' functionality and performance.

Figure 7.2. A synchronized system in which a global clock is used for both driving (device A) and receiving (device B) devices.

Propagation delays (PD) from clock to data latch inputs (T_c_pda, T_c_pdb) and data drive (device A) output to data receiver (device B) input (T_d_pd) are also shown.

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In this synchronized system, the initial clock pulse causes the driving device A to latch the data from the input and launch it into the transmission medium. The second clock causes device B to latch the incoming data. The time available for sending and receiving a data bit is one clock period T₀. Figure 7.3 shows the relationships between those critical timing parameters.

Figure 7.3. The relative relationships between the various timing parameters shown in Figure 7.2. Here T_su is the setup time, T_su_mg is the setup time margin, T_hd is the hold time, T_hd_mg is the hold time margin, and T₀ is the clock period.

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Figure 7.3 suggests the following relationships for these timing parameters:

Equation 7.2

Equation 7.3

These two equations can be rewritten in a different format:

Equation 7.4

Equation 7.5

Let us define T_{c_skew} = T_{c_pda} – T_{c_pdb}. The minimum conditions are that both setup time and hold time margin should be larger than 0.

This leads to the following inequalities for setup and hold time conditions:

Equation 7.6

Equation 7.7

Equations 7.6 and 7.7 give the quantitative descriptions of how clock jitter and clock skew affect the performance of the synchronized system in which a common or global clock for both driver and receiver is used.

In the absence of clock jitter (T_{c_jitt} = 0), if T_{c_skew} > 0, the minimum clock period increases, degrading system performance. Under this condition, the maximum hold time also increases, making the hold time condition easy to meet. On the other hand, if Tc_skew < 0, the minimum clock period decreases, improving system performance. Under such conditions, the maximum hold time deceases, making the hold time condition harder to meet (a race condition).

In the absence of skew (T_{c_skew} = 0), if T_{c_jitt} > 0 (longer cycle), the minimum clock period increases, degrading system performance.

Meanwhile, under this same condition, the maximum hold time decreases, making the hold time condition hard to meet. So positive jitter over one clock period makes both clock period and hold time hard to meet. If T_{c_jitt} < 0 (a shorter cycle), the minimum clock period decreases, improving system performance. Under this condition, the maximum hold time increases, making the hold time condition easier to meet and eliminating race conditions. You can see that a longer cycle does more harm to system performance.

When both skew and jitter are present, system performance can be any of the four scenarios just discussed. If skew is the dominant effect, the discussions of skew impact continue to hold. Similarly, if jitter is dominant over skew, the discussions of jitter impact continue to hold. When jitter and skew are comparable, quantitative numbers for both jitter and skew are needed to assess the net effect on system performance.

7.1.2.2. Asynchronized System

We have discussed both skew and jitter effects on system performance for a synchronized system. Using link I/O as an example, the skew for a synchronized system becomes hard to manage when the data rate increases, typically above 1 Gb/s. At multiple Gb/s data rates, an asynchronized system is commonly used, as shown in Figure 7.4.

Figure 7.4. A block diagram of an asynchronized link system. Note that there is no global clock, as in the case of the synchronized system shown in Figure 7.2.

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Unlike a synchronized system, this asynchronized link system does not send clock with data to the receiver. Instead, only data bit stream is sent. The clock is embedded in the data signal and gets recovered at the receiver through a unit called clock recovery (CR).

Obviously, this asynchronized link system has no clock skew, because clock at the receiver is not distributed or sent, but rather is recovered. Phase-locked loop (PLL) is typically used to recover the clock from the incoming data stream.

Let us assume that the jitter for the transmitter clock and recovered clock are composed of DJs and RJs. Further assume that the DJ and RJ for the transmitter clock after the high-pass filter of the clock recovery jitter transfer function^[6] (see Chapters 9, 10, and 11) are DJ_{clk_tx} for its pk-pk and σ_{clk_tx} for its Gaussian sigma or rms, respectively. Similarly, for the recovered clock, we assume that its DJ pk-pk and RJ Gaussian sigma are DJ_{clk_rx} and σ_{clk_rx}, respectively. Let us also assume that the jitter from the transmitter clock and jitter from the recovered clock are independent. Then the worst-case jitter at the receiver eye closure due to clock jitter is as follows:

URL http://access.proquest.safaribooksonline.com/9780132429610/ch07lev1sec1 Equation 7.8

Equation 7.9

The jitter from the transmitter clock and recovered clock both impact the receiver eye closure according to equations 7.8 and 7.9. They both need to be minimized to achieve good overall system performance. Low-frequency jitter from the transmitter clock can be tracked or attenuated by the clock recovery function if it has a high-enough corner frequency. A low phase noise oscillator within a PLL clock recovery also provides smaller RJ generations. These are two obvious design guides for reducing jitter from both the transmitter clock and receiver recovered clock if cost is not a constraint.

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Information Theory Computer Science Mike Peng Li Prentice Hall Jitter, Noise, and Signal Integrity at High-Speed