The frequency synthesizer is implemented in TSMC 0.18µm CMOS technology and is based on the ZigBee synthesizer of Chapter II that was also reported in [4]. The syn- thesizer of Chapter II employed a TSPC prescaler in its programmable dividers and the TSPC dual-modulus prescaler consumed 2.6mW in 0.18µm technology. However, the large capacitance of TSPC circuits' input-clock path resulted in an additional 2.6mW of buer power. To solve this problem and improve the total power consump-
tion, the proposed new PLL employs a DCVSL-R based dual-modulus prescaler. Fig. 37 shows the PLL block diagram. The center frequencies of 16 ZigBee chan- nels in the targeted band are in the range from 2.405GHz to 2.48GHz and are spaced by 5MHz, which is the reference frequency of this PLL. The divide-by-4 circuit before the PFD is employed to minimize the eect of coupling from external reference signal to the sensitive nodes of the PLL and to reduce resulting spurs. Then, the strong external reference signal is at 20MHz, and the desired reference frequency of 5MHz is generated by the internal divide-by-4 circuit. Therefore, any coupling from the strong input clock pin and routing to the PLL control node within the microchip and on the PC board will be pushed to appear at 20MHz oset, where spur suppression will be better than it would be at 5MHz oset.
Fig. 37. Block diagram of the new PLL with DCVSL-R divider
The LC-tank VCO operates at twice the channel frequency range (4.81GHz - 4.96GHz). A divide-by-2 circuit generates quadrature LO signals to be used by up/down conversion mixers of a transceiver. This divide by 2 circuit is implemen-
ted with CML instead of DCVSL-R circuit for quadrature signal generation with very small IQ mismatch and with smaller controlled swing rather than the rail-to-rail swing of DCVSL-R circuit, to provide smaller swing at the LO to improve mixer linearity.
As discussed in Chapter II, on system level the pulse-swallow divider consists of a 5-bit programmable (P ) counter, 4-bit channel selections (S counter), and a 15/16 dual-modulus prescaler. The overall programmable division ratio of the pulse-swallow divider is given by N:
N = 481, 482, ..., 495, 496 (4.1)
The prescaler speed limitation arises during /15 operation, which employs the divide-by-3 mode of the /3 or /4 circuit. The critical delay path in the /3 circuit and the timing condition that the circuit should satisfy is given by:
T DDF F 2_Slave+ 2 × T DN OR2 ≤
TCLK
2 (4.2)
where T DDF F 2_Slave is the delay of the slave latch of the second ip- op, T DN OR2
is the delay of the two input NOR gate and T DCLK is the input clock period of
the prescaler. The delay values T D include not only the propagation delay of those circuits but also the corresponding setup and hold times. Note that F IN is the highest frequency in the divider and therefore half of it's period sets a very strict time limitation on the divide-by-3 circuit.
In this synthesizer, the ip- ops and gates shown in Fig. 12 are implemented with DCVSL-R structure. Fig. 38 shows the D ip- op implementation based on DCVSL- R and use high-resistivity poly resistors. The layout of the prescaler is shown in Fig. 39 where the whole 15/16 prescaler takes 71µm × 24µm area. Note that there are two additional dummy resistors, one for each side, for matching purposes. Also note
that despite the addition of resistors, the total area of the prescaler is very small due to the reduced capacitance and stacking, small transistor sizing is used. The TSPC prescaler designed in Chapter II in the same technology takes 128.5µm×18.5µm area. Since the operating frequency falls down to a few hundred MHz frequency range at the output of the prescaler, the P and S counters are implemented with standard complementary CMOS logic.
Fig. 38. Circuit level diagram of D ip- ops used in the DCVSL-R based prescaler
B. Measurement Results
The frequency synthesizer is fabricated in TSMC 0.18µm CMOS, mounted on an FR-4 PCB, and measured. An on-chip open-drain buer measures the PLL output. Table XI summarizes the PLL measurement results.
Table XI. Measured performance summary of the frequency synthesizer Frequency Synthesis 2.405GHz - 2.48GHz
VCO Frequency 4.4GHz - 5.22GHz
Technology 0.18µm CMOS
Spur Suppression -48 dBc at 5MHz oset -55 dBc at 10MHz oset Phase Noise -135 dBc/Hz at 10MHz oset
-127 dBc/Hz at 3.5MHz oset
Settling Time 58µs
Power Consumption 8.3mW
Area 0.56 mm2
The PLL output frequency spectrum is shown for the rst channel, 2.405GHz operation, in Fig. 40. Spur suppression at this channel at 10MHz oset frequency is -55dBc/Hz. Fig. 41 illustrates the phase noise performance of the closed loop PLL for 2.405GHz while Fig. 42 shows the phase noise plot at 2.48GHz. Note that the phase noise is -135dBc/Hz at 10MHz oset frequency and it is -127dBc/Hz at 3.5MHz oset.
Fig. 40. Output frequency spectrum of the new synthesizer with DCVSL-R dividers at 2.405GHz
Fig. 43 displays the die micrograph, where the PLL occupies an area of 0.8mm by 0.7mm. The settling time is shown in Fig. 44 where the settling time is 58µs and the overshoot is % 28.5. The synthesizer consumes 8.3mW total power. Note that operating the VCO at double the channel frequency increases the power consumption of the PLL. This is due to the generation of quadrature LO signals for ZigBee which employs OQPSK modulation.
Fig. 41. Phase noise spectrum of the new synthesizer at 2.405GHz
Fig. 43. Die micrograph of the new PLL