amplitude of the pulser signal was increased by hand after about 10000 counts have been acquired.
The result is shown in figure B.4 for two different designs, the first one uses a1616
multiplier and the second a 2424 multiplier. The design using the1616 multiplier
is clearly inferior compared to the one using the 24 24 multiplier and this could be
due to the implementation of the 16 16 MWD, which has to be verified in further
tests. The deviation of the pulser peak position from the function value is very large and even a quadratic fit does not improve the result. Therefore the design using the
2424 multiplier is the preferred implementation and was consequently used for the
measurements with the detectors.
B.5.1 Changing the ADC clock
The AD6645-80 ADC supports a minimum conversion rate of 30 MHz and a maximum conversion rate of 80 MHz. Since the ADC clock is generated by the FPGA a special VHDL code variant was written that reduces the ADC clock from 80 to 40 MHz. The result is shown in the figure B.6. One can clearly see that the decay time of the pulser seems to be different because the time difference between each sample is 12.5 and 25 ns in the upper and the lower panel, respectively.
Since the Nyquist filter is fixed to 40 MHz, the possibility to change the ADC clock is not very useful. Using a Nyquist filter set to 20 MHz, which is considered sufficient for current HPGe preamplifiers, would allow to switch between 40 and 80 MHz conversion frequency depending on the detector type connected to the GRT4. On the other hand, the preamplifiers for HPGe detectors already limit the bandwidth to about 20-30 MHz, i.e. a Nyquist filter might not be necessary since the signal power at high frequencies is very low14.
For slow detectors the 40 MHz conversion frequency also allows an increase of the shaping times by a factor of two without occupation of more block RAMs. For faster detectors like silicon strip detectors or inorganic scintillation detectors, the 80 MHz sampling frequency allows the analysis of the pulse shape15. However, since the GRT4 module was designed for the purpose of scanning highly segmented HPGe detectors, the operation at 80 MHz is mandatory and was used for the measurements in the following sections.
B.6
MWD implementation for the DDC-8 module
The MWD implementation was tailored to the DDC-8 module [109], which can be used as a daughter card for the XLM-80 VME module and was considered as an electronics for the MINIBALL DSSSD detector. The DDC-8 features eight 10 bit 40 MHz ADC as well as one Spartan XC2S300E FPGA and can be read out using the USB connector.
In order to process all channels in parallel without disturbing interference, the trig- ger and state machine were generated eight times. However, for the energy branch a more efficient implementation was chosen. For this, the data from the ADC, coming
14If the response of the Nyquist filter is slow it allows the measurement of signal which are shorter than
Ts, since the fast signal loads the capacitance of the filter which in turn discharges slowly.
15
-300 -200 -100 0 100 200 300 0 1 2 3 4 5 6 7 Position - f(x) [a.u.]
Pulse Height [a.u.] -300 -200 -100 0 100 200 300 0 1 2 3 4 5 6 7 Position - f(x) [a.u.]
Pulse Height [a.u.]
(a)1616multiplier with linear calibration
-150 -100 -50 0 50 100 150 200 0 1 2 3 4 5 6 7 Position - g(x) [channels]
Pulse Height [a.u.] -150 -100 -50 0 50 100 150 200 0 1 2 3 4 5 6 7 Position - g(x) [channels]
Pulse Height [a.u.]
(b)1616multiplier with quadratic calibration
-4 -3 -2 -1 0 1 2 3 4 0 2 4 6 8 10 Position - f(x) [a.u.]
Pulse Height [a. u.] -4 -3 -2 -1 0 1 2 3 4 0 2 4 6 8 10 Position - f(x) [a.u.]
Pulse Height [a. u.]
(c)2424multiplier with linear calibration
-2.5 -2 -1.5 -1 -0.5 0 0.5 1 0 2 4 6 8 10 Position - g(x) [a.u.]
Pulse Height [a. u.] -2.5 -2 -1.5 -1 -0.5 0 0.5 1 0 2 4 6 8 10 Position - g(x) [a.u.]
Pulse Height [a. u.]
(d)2424multiplier with quadratic calibration
Figure B.4: Linearity of the energy spectrum determined with a pulser. Two different MWD
implementations were tested using either a1616or a2424multiplier. The pulser
peak positions were fitted using a linear and a quadratic function and the residual, i.e. the difference between the peak position and the function value is plotted. The
2424multiplier achieves the best results and the quadratic expression fits better
B.6. MWD IMPLEMENTATION FOR THE DDC-8 MODULE 171 800 1600 2400 3200 4000 4800 5600 6400 0 1000 2000 1600 2400 3200 4000 4800 5600 6400 800 Sample Index Amplitude [a.u.]
Figure B.5: The signal from a pulse generator was sampled with 80 and 40 MHz. This was
possible with a modification to the VHDL code, because the ADC clock is generated by the DLL units in the Spartan 2 FPGA.
at a rate of 40 MHz, is first reduced by a decimation unit to a 10 MHz rate. Then all eight channels are consecutively processed at a 80 MHz rate by the energy filter (”octal pumped pipeline”) using a common peakingLand flat top timeM L, but separate decay
time parameters
1:::8. In this configuration the peaking time can be adjusted between
100 ns and 3.2 s. The BLR update frequency is usually only 500 kHz and a processing
of all eight channels can easily be achieved.
One of the most important components is the state machine, which allows an inde- pendent processing of all eight channels and is therefore present eight times. It does not feature any pile up rejection (non-extendable dead time model), but does detect a pile up condition. The state machine is connected to the associated fast trigger module (8 in total) and allows an independent latching of the corresponding energy and baseline filter values a fixed time after a trigger.
Figure B.6: MWD implementation for the DDC-8 module. Eight 10 bit 40 MHz ADC are pro-
cessed by a single Spartan2 XC2S300E FPGA by combining the decimated data (DEC unit) into a single stream (MUX unit) for the single trapezoidal filter and baseline module.