Improved Wide fan-in Domino OR gate-Dynamic node footed scheme

To avoid the capacitive loading problems, we go for this modified new technique. The following modified circuit fulfils our requirements. In spite of having few drawbacks, as a whole its results are better than most other techniques.

Modifications made:

(1) Reduction of the Transparency window (T delay) so that greater the noise robustness. (2) Insertion of NMOS transistor Mn between dynamic node and PDN.

Fig. 4.30 Improved Wide fan-in Domino OR gate-Dynamic node footed schematic implementation.

This modified circuit is simulated and corresponding simulation result is shown below.

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Fig. 4.31 Improved Wide fan-in Domino OR gate-Dynamic node footed schematic simulation.

From the simulation result, the leakage current was found to be 21.45 n.a. Advantages:

(1) High noise robustness. (2) Reduction of leakage current. (3) Low area over overhead. Disadvantages:

(1) Increased capacitive load of CLK line and increased resistance of discharging path of dynamic node due to presence of Mn and NMOS-externally inserted transistor. (2) Series of inverters, Mn, NMOS-externally inserted transistor all these cause dynamic

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TABLE 4.1 Leakage current comparisons among different techniques of Wide fan-in Domino OR gate.

Circuit technique Leakage current

Foot-less 25.49 n.a

Footed 257 n.a

Diode-footed 856 p.a

Replicated evaluation of PDN 34.7 p.a

Dynamic node footed 702 n.a

CLK delayed 266 n.a

SFEG 276 n.a

TABLE 4.2 Leakage current comparisons between Unmodified & Improved techniques of Wide fan-in Domino OR gate.

Circuit technique

Leakage current

Un-modified Improved

Footed 257 n.a 42 p.a

Footless 25.49 n.a 266.9 n.a

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CHAPTER 5

CONCLUSION

Domino CMOS logic circuit family finds a wide variety of applications in microprocessors, digital signal processors, and dynamic memory due to their high speed and low device count. Domino logic is a CMOS logic style obtained by adding a static inverter to the output of the basic dynamic gate circuit.

In this thesis, An introduction to domino logic, The impact of CMOS technology scaling on the performance of domino CMOS logic, Three Phase Domino Logic Circuit, High- performance noise-tolerant circuit techniques for CMOS dynamic logic and other Domino logic techniques are studied and corresponding Domino logic techniques have been designed & simulated. The results are studied. The advantages & disadvantages are also observed.

Advantages of Domino CMOS logic: (1) High speed

(2) Low device count. Disadvantages:

(1) Degradation of Noise immunity. (2) Inevitable leakage currents. (3) Charge sharing.

(4) Large power consumption.

In all those techniques the important effects like sub threshold leakage currents, threshold voltages, supply voltages, sources of noise, power consumptions, delays and area are considered. Few modifications have also been made to already existing domino techniques to get desired results. The improved techniques, though they suffer from few drawbacks, are giving better results compared with previous techniques.

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Different Domino logic circuits are simulated in both Cadence virtuoso (implemented using GPDK090- library of 90nm technology) and Mentor graphics (implemented at different technologies like Tsmc 035.mod, Tsmc 025.mod, Tsmc 018.mod) environments. The performance parameters of improved techniques are also compared with other standard architectures of Domino logic.

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