Inherent prognostic parameters

The major semiconductor failure mechanisms that can be monitored with inherent prognostic parameters are discussed here. Sometimes, the number of prognostic parameters for a particular failure mechanism is more than one. Most of these prognostic parameters are discussed in literature for laboratory study purposes, and an amount of commercially available equipment, such as curve tracers and semiconductor device analysers, are often used for parameter measurement. Examples of such equipment are the Agilent B1505A [84], the Tektronix 371B [85], the T3Ster [86], the 9624-KT Thermal Tester [87] and the Phase 11 Thermal Analyser [88]. However, for taking these parametric measurements, the electric circuitry of the inverter system needs to be changed, and to achieve a high degree of accuracy it is even needed to dissemble or destroy the inverter system. In addition, this equipment is normally costly and requires sophisticated software to operate. As a consequence, appropriate parameters for specified failure modes need to be carefully selected and their feasibility for on board EV application considered. These monitoring techniques can not be directly converted into real applications since their measurements require detailed practical considerations.

In this section, a selection of frequently used inherent prognostic parameters for laboratory studies are reviewed; further knowledge regarding device or packaging failure mechanisms is still under development. Their in-situ monitoring techniques will be further discussed in Chapter 5 and Chapter 6 in detail.

1) To detect TDDB and gate oxide degradation

Gate threshold voltage VGE,th, capacitance-voltage (C-V) [43, 54, 89, 90] and leakage current are measured to identify TDDB and gate oxide degradation by detecting changes in their electrical behaviour.

Gate threshold voltage is the lowest gate voltage at which IGBT turns on and a specified small amount of I_D begins to flow. The test is run by shortening the gate to the drain so that V_GS = V_DS and two general methods are used:

 Applying a voltage to the gate contact, monitoring the current through the dielectric layer (voltage test);

 Injecting a current from the gate and measuring the gate voltage needed to

CHAPTER 3 RELIABILITY, RROGNOSTICS AND HEALTH MONITORING

sustain such current (current test);

Figure 3.3 Degradation progress as observed on threshold voltage [89]

The changes in threshold voltage under defined drain current and temperature (as shown in Figure 3.3) are observed in the published literature [43, 54, 89, 90]. This is correlated with the presence of trapped electrons in the gate oxide, which was verified by the Capacitance-Voltage (C-V) measurements conducted in the work of Patil and et al [54].

The C-V plot translates to the right if the oxide trapped charge is negative, and to the left if the trapped charge is positive [91]. Holes trapped in the gate oxide lead to a negative threshold shift, while trapped electrons lead to a positive threshold shift. For all the parts in Patil’s research [54], a right shift in the C-V measurements was observed, showing the presence of trapped electrons in the gate oxide as a result of aging (Figure 3.4).

Figure 3.4 C-V measurement [54]

CHAPTER 3 RELIABILITY, RROGNOSTICS AND HEALTH MONITORING

As observed in Patil’s experiment [54] (Figure 3.5), the threshold voltage has negative temperature dependency for both aged and new devices. This is because the increase in temperature leads to a decrease in the band-gap of the silicon, which reduces the threshold voltage.

Figure 3.5 Threshold voltage variation with temperature [54]

2) To detect the bond wire lift-off and chip metallization reconstruction

Optical microscope imaging can be used to check the crack at the bond wire interface and the rough level of chip metallization. The shear stress test is an alternative, commonly used approach to quantify the degradation condition between the bond wires and chip metallization. However, both approaches are off-line tests and always lead to device destruction. The forward voltage drop VCE(on) / VF or resistance Ron are traditionally used to detect the bond wires or emitter metallization damage [92]. Their increases are mainly due to degradation of the bond wires and their interface to the metalized top side of silicon. Chip metallization reconstruction leads to the reduction of the effective cross section of the metallization layer, which could also contribute to increased electrical resistance [46]. The aging failure criterion proposed for bond wire lift-off, which is generally accepted as the end-of-life on IGBT modules, is a 5%

increase of the on-state voltage V_CE(on) / forward voltage V_F with respect to its initial value at fixed conducting current and junction temperature [42, 63, 93-95]. The relative variations due to this damage are very low because the voltage across the connections constitutes a weak part of the total on-state voltage. Therefore, this measurement must be made with a very high degree of accuracy.

CHAPTER 3 RELIABILITY, RROGNOSTICS AND HEALTH MONITORING

3) To detect the thermal path degradation

Degradations in the assembly integrity between IGBT die and baseplate, most frequently in the DCB substrate and solder layers, can hinder heat conductivity and lead to the deterioration of the thermal path. In [96, 97], scanning acoustic microscope (SAM) images are used to evaluate DCB solder layer condition and detect solder fatigue in terms of voids, cracks, and delaminations. SAM is an equipment which uses ultrasonic sound waves and the echoed signal to investigate, measure, or image an object, and it is based on the principle that propagation and reflection of acoustic waves change at interfaces where a change of acoustic impedance occurs. Cracks and voids usually lead to a stronger echo. By scanning over the desired area, the microscope converts the signal into a greyscale image in which voids and cracks appear brighter than the intact solder [43]. However, this method is an off-line test and usually used in the laboratory to check DCB solder layer fatigue. Furthermore, it is difficult to quantify die-attach (chip solder) degradation. To achieve an in-situ assessment of the thermal path condition (mainly for die-attach and DCB solder), approaches relating to thermal characterizations are widely used and thermal impedance is taken as a desired precursor.

It is nonintrusive, can be performed for in-situ applications and it also has an advantage in evaluating the thermal condition of assembly, which is of significance for thermal safety. However, in-situ measurement requires detailed considerations, which will be discussed in Chapter 4.3 in detail.

4) To detect other degradation

The level of partial discharge is indicative of insulation failure within silicon gel, caused by environmental stresses like high temperature and high moisture [98].

Since this thesis focuses on the two most significant failure modes due to thermal aging:

bond wire lift-off and solder fatigue, forward voltage drop and thermal impedance are used as precursors and they are frequently measured to evaluate the health of power modules.