Note: The Intel MAC/PHY silicon devices (82558, 82559, 82550, and 82551) use the 82555 as the base for their integrated PHY units. Therefore, the information contained in this section and the following subsections apply to the all 8255x Fast Ethernet controllers except the 82557.
7.3.1 Status and Control Register: Register 16
Bit Name R / W Description Default
15 Flow Control RW
1 = Flow control enabled.
0 = Flow control disabled.
NOTE: This bit should always equal 0 for the 82559.
0
14 T4 Enable RW
This bit enable T4 when auto-negotiation is disabled.
1 = Enable T4 technology 0 = Disable T4 technology
0
13 CRS Disconnect Control RW
This bit controls the RX100 CRS disconnect function in repeater mode.
NOTE: This bit should always equal 0 for the 82559.
0 = DTE 1 = Rptr
12 Reserved This bit is reserved. 0
11 RCV De-Serializer
In-Sync Indication RO This bit is used as the 100BASE-TX RCV
De-Serializer In Sync Indication 0
10 100 Power Down RO
This bit provides 100BASE-T Power Down Indication.
1 = Power down 0 = Normal operation
0
9 10 Power Down RO
This bit provides 10BASE-T Power Down Indication.
7:3 Reserved These bits are reserved. 0
2 T4 RO
This bit is a result of the auto-negotiation process.
1 = 100BASE-T4.
0 = No 100BASE-T4
0
1 Speed RO
This bit is a result of the auto-negotiation process.
1 = 100 Mbps 0 = 10 Mbps
0
0 Duplex RO
This bit is a result of the auto-negotiation process.
1 = Full duplex 0 = Half duplex
0
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7.3.2 Special Control Register: Register 17
Bit Name R / W Description Default
15 Scrambler Bypass RW 1 = Bypass Scrambler
0 = Normal operation 0
14 4/5 Bypass RW 1 = Bypass 4-bit to 5-bit
0 = Normal operation 0
13 Force Transmit H Pattern RW 1 = Force H pattern
0 = Normal operation 0
12 Force 34 Transmit Pattern RW 1 = Force 34 pattern
0 = Normal operation 0
11 Good Link RW
1 = 100BASE-TX good link indication, forcing to ASD output
0 = Normal operation
0
9 MDI Tristate RW 1 = Tri-state MDI interface
0 = Normal operation 0
8 Dynamic Power Down
Disable RW 1 = Disable Dynamic Power Down.
0 = Normal operation 0
7 Auto-Negotiation
Loopback RW 1 = Auto-negotiation loopback
0= Auto negotiation normal Mode. 0
6 Reserved This bit is reserved. 0
5 Filter Bypass RW 1 = Bypass filter
0 = Normal operation 0
4 Auto-Polarity Disable RW 1 = Disable auto-polarity
0 = Normal operation 0
3 Squelch Test Disable RW 1 = Disable 10BASE-T squelch test
0 = Normal squelch operation 0
2 Extended Squelch RW This bit indicates extended squelch control 0
1 Link Integrity Disable RW 1 = Disable link integrity operation
0 = Normal link integrity operation 0
0 Jabber Function disable RW 1 = Disable jabber function
0 = Normal jabber operation. 0
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7.3.3 Clock Synthesis Test and Control Register: Register 18
7.3.4 100BASE-TX Receive False Carrier Counter: Register 19
7.3.5 100Base-TX Receive Disconnect Counter: Register 20
Bit Name R / W Description Default
15 Clock Timing RW
SC
Clock Synthesizer Shift command. One shot signaling YS10ACLK domain.
Can be active only when bit 14 is ‘0
14 Clock Timing RW
SC
Clock Synthesizer load command. One shot signaling YS10ACLK domain.
Can be active only when bit 15 is ‘0 13 Break Down Timer
Enable RW Logic 1 enables manipulate Break Down counter with phya1, phya4 and test high.
12 Equalizer Probe Mode
Enable Logic 1 enables the Equalizer output through the
Speed LED. 0
11 10BASE-T Probe Mode
Enable RW 1 = Enable 10BASE-T dig outputs through the LEDs
NOTE: This function is only present on the 82559.
0
10:8 Reserved These bits are reserved. 0
4:0 PHY Address RO This field contains the PHY address. 00001
Bit Name R / W Description Default
15:0 Receive False Carrier RO SC
This register contains a 16-bit counter for false carrier events. A false carrier event occurs when a frame that does not start with “JK” is detected.
When the counter is full, additional false carrier events are not counted. This counter is self-clearing on read.
0
Bit Name R / W Description Default
15:0 Disconnect Event RO
SC
This register contains a 16-bit counter for disconnect events. The counter is incremented for each frame detected in repeater mode that does not start with a “JK.” When the counter is full, additional disconnect events are not counted. This counter is self-clearing on read.
0
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7.3.6 100BASE-TX Receive Error Frame Counter: Register 21
7.3.7 Receive Symbol Error Counter: Register 22
7.3.8 100BASE-TX Receive EOF Error Counter: Register 23
7.3.9 10BASE-T Receive EOF Error Counter: Register 24
7.3.10 10BASE-T Transmit Jabber Detect Counter: Register 25
Bit Name R / W Description Default
15:0 Receive Error Frame RO SC
This register contains a 16-bit counter for receive error frames. It is incremented for frames with a receive error condition (frames containing a symbol error or frames with a premature end of frame).
When the counter is full, additional error frames are not counted. This counter is self-clearing on read.
0
Bit Name R / W Description Default
15:0 Symbol Error RO
SC
This register contains a 16-bit counter and increments for each symbol error. The counter stop counting additional symbol errors when it is full.
This counter is self-clearing on read.
0
Bit Name R / W Description Default
15:0 Premature End of Frame RO SC
This register contains a 16-bit counter and increments for each premature end of frame event.
It stops counting additional premature end of frame events when it is full. It is self-clearing on read.
0
Bit Name R / W Description Default
15:0 End of Frame RO
SC
This register is a 16-bit counter that increments for each end of frame error event. The counter stops counting additional errors when it is full. It is self-clearing on read.
0
Bit Name R / W Description Default
15:0 Jabber Detect RO
SC
This register is a 16-bit counter that increments for each jabber detection event. The counter stops counting additional events when it is full. It is self-clearing on read.
0
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7.3.11 Equalizer Control and Status Register: Register 26
This register is used to control and monitor the operation of the 8255x PHY module equalizer (excluding the 82557 since it does not have an integrated PHY unit). Bits 15:13 specify the command, and bits 12:0 contain the data field for the command.
Bit Name R / W Description Default
15:0 Equalizer Control and
Status RW Bits 15:13 contain the opcode command while bits 12:0 hold the command data.
Opcode Command (bits 15:13) Command Data (bits 12:0) 000 NOP
001 Write to ASD configuration register 0
[12] Set zero command. Set value of bits 3:0.
[11:10] FSM high threshold transitions:
00 = FM: 2.19 ms; SM: 2.01 ms (0.5 ms - 2.03 ms) 01 = 2.19 ms
10 = FM:2.19; SM:2.03 (0.5 ms - disabled) 11 = Disabled
[3:0] Coded zero 0 through 15.
010 Write to ASD configuration register 1
[12:11] Reserved.
[10:9] TMD100 transition ration bits/LPF ratio:
00 = 0.5 / 6 01 = 0.5 / 5 10 = 0.25 / 6 11 = 0 / 6
[8:7] Signal detect 5-bit counter setting value:
00 = 10h 01 = 18h 10 = 1Ch 11 = 1Fh
[6] Set signal detect counter command.
[5] Reserved.
[4] Disable lock adaptation mechanism.
[3:1] Reserved.
[0] Force test mode and activate LFSR register.
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7.3.12 Special Control Register: Register 27
011 Write to ASD configuration register 2
[9] Breakdown ASD counters.
[8] Selects signal detections or transitions.
[7:6] Slow mode adaptation time configure:
00 = 67 ms (default)
[1] Disable signal detect high threshold value.
[0] Disable signal detect low threshold value.
100 Read status register
[15:0] Reflects the jitter register bits.
Write cycle:
[1:0] Selects the register lines reflected by read.
00 = Bits 15:0
[0] Selects the window reflected by read.
0 = 15:0 1 = 23:8 111 Reserved
Bit Name R / W Description Default
15:0 Special Control Register RW Bits 15:3 are reserved, and bits 2:0 are used for the LED switch control.
Opcode Command (bits 15:13) Command Data (bits 12:0)
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