Inter-processor communication

The communication between the MicroBlaze processors and the PowerPC processor is accomplished using the shared memory. Basically, the behavior to send some information is the same for both parties. The data acting as parameters for an instruction or as return values is written into predetermined memory locations. To actually trigger the

7.7. Inter-processor communication

communication, a bit code signifying the type of the communication is written to another memory location, which is repeatedly read by the receiving party in a busy waiting manner.

Busy waiting is usually avoided, because it wastes processor cycles, which could be used for useful computations. Instead, an interrupt approach may be used, in which the receiving party is notified about the message by means of an interrupt. After this, the receiver copies the data to its memory, acknowledges the reception, and continues the execution at that point of execution, at which it was interrupted.

In the prototype implementation, this approach was not adopted, because the proces- sor, which is busy waiting for some information, usually has nothing else to do, thus, no cycles are wasted. This is especially true, for the MicroBlaze processors, whose only task is the execution of scheme calculations. The PowerPC, on the other hand, has to communicate with multiple soft-cores and the host system. However, it is significantly faster than the soft-cores and has a significantly smaller work load. Therefore, it is waiting most of the time. Finally, because the operations, which are required to ac- knowledge a scheme result and to issue the next one, are relatively small and because of the proof-of-concept nature of the prototype, it was decided to accept this small delay.

Although the PowerPC could theoretically access the complete data memories of the MicroBlaze processors, only a part of each is utilized as shared memory. The remainder is used as normal data memory for the soft-cores. This is accomplished by instructing the linker to leave some area unoccupied. Thus, the code of both processor types has complete control over it. Therefore, it is also not initialized by compiler generated code, but this is instead performed by the MicroBlaze processors, which fill this area with 0 at start up time.

As depicted in Figure 7.21, this initialization is followed by a handshake with the PowerPC. This handshake provides each soft core with an unique processor ID and guarantees the PowerPC that the MicroBlaze processors have entered the busy waiting state, thus, commands to compute cryptographic schemes may be issued.

The flow of the inter-processor communication is depicted in Figure 7.22. As part of the initialization described above, the MicroBlaze processor sets the memory locations COMMAND and RESULT to their neutral values. In this context, COMMAND denotes the location, into which the PowerPC may write commands for the soft-core. RESULT may be used by the scheme controller to send replies for the central core. After this, the MicroBlaze processor starts busy waiting for commands from the PowerPC. In contrast, latter one interprets the setting of the neutral values as sign that the soft-core is ready to receive commands and starts executing its own program.

The basic flow of one scheme execution is as follows: The PowerPC writes a new opcode distinct from NOP, see Section 7.5.3, into COMMAND. This is observed by the MicroBlaze processor, which subsequently starts executing the desired scheme. During this time the central core is busy waiting for the reply from the scheme controller. This reply – either SUCCESS or ERROR – is written into RESULT by the soft-core after the completion of the scheme. After the PowerPC receives the reply, it acknowledges it by setting both memory locations to their neutral values and continues with its program. The soft-core, in turn, interprets this acknowledgment as signal to start busy waiting

Chapter 7. Prototype implementation

Set processor ID and set status INIT_RESPONSE

Wait for status INIT

FINALIZE Set status WAIT_FINALIZE

Wait for status

Initialize memory with 0

Set status INIT

Wait for status INIT_RESPONSE

WAIT_FINALIZE Set status

FINALIZE Wait for status

Set status NOP PowerPC MicroBlaze initialization Start of End of initialization Start of initialization End of initialization

Figure 7.21.: Initialization of the shared memory

for new commands again.

The memory locations COMMAND and RESULT are both part of the second memory location of the shared memory, see Table 7.13. This location has a length of 4 bytes and its least significant byte is used by the PowerPC as COMMAND. The most significant nibble of this location is utilized as RESULT.

The complete configuration of the shared memory is depicted in Table 7.13. The first location contains the processor ID, which is set during start up. The second location is utilized for the communication between the processors, as described above. The third location is used to transfer the domain parameters for either RSA or ECC schemes. Debug messages from the MicroBlaze processors may be written to the fourth location. They are read by the PowerPC, whenever is notified about their presence using a special value in the location RETURN. Then, the PowerPC sends the message on to the host system via the UART interface. The message to be de-/encrypted or signed/verified is