Interconnect Parameters — Capacitance, Resistance, and Inductance

4.3.1 Capacitance

An accurate modeling of the wire capacitance(s) in a state-of-the-art integrated circuit is a non-trivial task and is even today the subject of advanced research. The task is compli- cated by the fact that the interconnect structure of contemporary integrated circuits is three-dimensional, as was clearly demonstrated in the process cross-section of Figure 2.8. The capacitance of such a wire is a function of its shape, its environment, its distance to the substrate, and the distance to surrounding wires. Rather than getting lost in complex equations and models, a designer typically will use an advanced extraction tool to get pre- cise values of the interconnect capacitances of a completed layout. Most semiconductor manufacturers also provide empirical data for the various capacitance contributions, as measured from a number of test dies. Yet, some simple first-order models come in handy to provide a basic understanding of the nature of interconnect capacitance and its parame- ters, and of how wire capacitance will evolve with future technologies.

Consider first a simple rectangular wire placed above the semiconductor substrate, as shown in Figure 4.3. If the width of the wire is substantially larger than the thickness of the insulating material, it may be assumed that the electrical-field lines are orthogonal to the capacitor plates, and that its capacitance can be modeled by the parallel-plate capaci- Figure 4.2 Wire models for the circuit of Figure 4.1. Model (a) considers most of the wire parasitics (with the exception of inter-wire resistance and mutual inductance), while model (b) only considers capacitance.

tor model (also called area capacitance). Under those circumstances, the total capacitance of the wire can be approximated as1

(4.1) where W and L are respectively the width and length of the wire, and t_di and ε_di represent the thickness of the dielectric layer and its permittivity. SiO₂ is the dielectric material of choice in integrated circuits, although some materials with lower permittivity, and hence lower capacitance, are coming in use. Examples of the latter are organic polyimides and aerogels. ε is typically expressed as the product of two terms, or ε = ε_rε₀. ε₀ = 8.854 × 10- 12 _{F/m is the permittivity of free space, and ε}

r the relative permittivity of the insulating material. Table 4.1 presents the relative permittivity of several dielectrics used in inte- grated circuits. In summary, the important message from Eq. (4.1) is that the capacitance is proportional to the overlap between the conductors and inversely proportional to their separation.

1_{To differentiate between distributed (per unit length) wire parameters versus total lumped values, we} will use lowercase to denote the former and uppercase for the latter.

Table 4.1 Relative permittivity of some typical dielectric materials.

Material εr Free space 1 Aerogels ~1.5 Polyimides (organic) 3-4 Silicon dioxide 3.9 Glass-epoxy (PC board) 5

Silicon Nitride (Si3N4) 7.5 Alumina (package) 9.5

Silicon 11.7

Dielectric

Substrate Figure 4.3 Parallel-plate capacitance model of interconnect wire.

L W H t_di Electrical-field lines Current flow c_int εdi t_di ---WL =

In actuality, this model is too simplistic. To minimize the resistance of the wires while scaling technology, it is desirable to keep the cross-section of the wire (W×H) as large as possible — as will become apparent in a later section. On the other hand, small values of W lead to denser wiring and less area overhead. As a result, we have over the years witnessed a steady reduction in the W/H-ratio, such that it has even dropped below unity in advanced processes. This is clearly visible on the process cross-section of FIG- URE. Under those circumstances, the parallel-plate model assumed above becomes inac- curate. The capacitance between the side-walls of the wires and the substrate, called the fringing capacitance, can no longer be ignored and contributes to the overall capacitance. This effect is illustrated in Figure 4.4a. Presenting an exact model for this difficult geome-

try is hard. So, as good engineering practice dictates, we will use a simplified model that approximates the capacitance as the sum of two components (Figure 4.4b): a parallel-plate capacitance determined by the orthogonal field between a wire of width w and the ground plane, in parallel with the fringing capacitance modeled by a cylindrical wire with a dimension equal to the interconnect thickness H. The resulting approximation is simple and works fairly well in practice.

(4.2) with w = W - H/2 a good approximation for the width of the parallel-plate capacitor. Numerous more accurate models (e.g. [Vdmeijs84]) have been developed over time, but these tend to be substantially more complex, and defeat our goal of developing a concep- tual understanding.

To illustrate the importance of the fringing-field component, Figure 4.5 plots the value of the wiring capacitance as a function of (W/H). For larger values of (W/H) the total capacitance approaches the parallel-plate model. For (W/H) smaller than 1.5, the fringing

Figure 4.4 The fringing-field capacitance. The model decomposes the capacitance into two contributions: a parallel-plate capacitance, and a fringing capacitance, modeled by a cylindrical wire with a diameter equal to the thickness of the wire.

w H

+

(a) Fringing fields

(b) Model of fringing-field capacitance. cfringe cpp c_wire c_pp+c_fringe wεdi t_di --- 2πεdi t_di⁄H ( ) log --- + = =

component actually becomes the dominant component. The fringing capacitance can increase the overall capacitance by a factor of more than 10 for small line widths. It is interesting to observe that the total capacitance levels off to a constant value of approxi- mately 1 pF/cm for line widths smaller than the insulator thickness. In other words, the capacitance is no longer a function of the width.

So far, we have restricted our analysis to the case of a single rectangular conductor placed over a ground plane. This structure, called a microstripline, used to be a good model for semiconductor interconnections when the number of interconnect layers was restricted to 1 or 2. Today’s processes offer many more layers of interconnect, which are packed quite densely in addition. In this scenario, the assumption that a wire is completely isolated from its surrounding structures and is only capacitively coupled to ground, becomes untenable. This is illustrated in Figure 4.6, where the capacitance components of a wire embedded in an interconnect hierarchy are identified. Each wire is not only coupled to the grounded substrate, but also to the neighboring wires on the same layer and on adja- cent layers. To a first order, this does not change the total capacitance connected to a given wire. The main difference is that not all its capacitive components do terminate at the grounded substrate, but that a large number of them connect to other wires, which have dynamically varying voltage levels. We will later see that these floating capacitors form not only a source of noise (crosstalk), but also can have a negative impact on the perfor- mance of the circuit.

In summary, inter-wire capacitances become a dominant factor in multi-layer inter- connect structures. This effect is more outspoken for wires in the higher interconnect lay- ers, as these wires are farther away from the substrate. The increasing contribution of the inter-wire capacitance to the total capacitance with decreasing feature sizes is best illus- trated by Figure 4.7. In this graph, which plots the capacitive components of a set of paral- lel wires routed above a ground plane, it is assumed that dielectric and wire thickness are Figure 4.5 Capacitance of interconnect wire as a function of (W/tdi), including fringing-field effects (from [Schaper83]). Two values of H/tdi are considered. Silicon-dioxide with εr = 3.9 is used as dielectric. W/T_di C a p a c it a n c e ( p F /c m ) _H/t di = 1 H/t_di = 0.5 C_p-p

held constant while scaling all other dimensions. When W becomes smaller than 1.75 H, the inter-wire capacitance starts to dominate.

sign Data

A set of typical interconnect capacitances for a standard 0.25 µm CMOS process are given in Table 4.2. The process supports 1 layer of polysilicon and 5 layers of Aluminum. Metal layers 1 to 4 have the same thickness and use a similar dielectric, while the wires at metal layer 5 are almost twice as thick and are embedded in a dielectric with a higher permittivity. When placing the wires over the thick field oxide that is used to isolate different transistors, use the “Field” column in the table, while wires routed over the active area see a higher capacitance as seen in the “Active” column. Be aware that the presented values are only indicative. To obtain more

Interconnect Capacitance Design Data

Figure 4.6 Capacitive coupling between wires in interconnect hierarchy.

fringing parallel

Figure 4.7 Interconnect capacitance as a function of design rules. It consists of a capacitance to ground and an inter-wire capacitance (from [Schaper83]).

accurate results for actual structures, complex 3-dimensional models should be used that take the environment of the wire into account.

Table 4.3 tabulates indicative values for the capacitances between parallel wires placed on the same layer with a minimum spacing (as dictated by the design rules). Observe that these numbers include both the parallel plate and fringing components. Once again, the capacitances are a strong function of the topology. For instance, a ground plane placed on a neighboring layer terminates a large fraction of the fringing field, and effectively reduces the inter-wire capacitance. The polysilicon wires experience a reduced inter-wire capacitance due to the smaller thickness of the wires. On the other hand, the thick Al5 wires display the highest inter- wire capacitance. It is therefore advisable to either separate wires at this level by an amount that is larger than the minimum allowed, or to use it for global signals that are not that sensitive to interference. The supply rails are an example of the latter.

Table 4.2 Wire area and fringe capacitance values for typical 0.25 µm CMOS process. The table rows represent the top plate of the capacitor, the columns the bottom plate. The area capacitances are expressed in aF/µm2, while the fringe capacitances (given in the shaded rows) are in aF/µm.

Field Active Poly Al1 Al2 Al3 Al4

Poly 88 54 Al1 30 41 57 40 47 54 Al2 13 15 17 36 25 27 29 45 Al3 8.9 9.4 10 15 41 18 19 20 27 49 Al4 6.5 6.8 7 8.9 15 35 14 15 15 18 27 45 Al5 5.2 5.4 5.4 6.6 9.1 14 38 12 12 12 14 19 27 52

Table 4.3 inter-wire capacitance per unit wire length for different interconnect layers of typical 0.25 µm CMOS process. The capacitances are expressed in aF/µm, and are for minimally-spaced wires.

Layer Poly Al1 Al2 Al3 Al4 Al5

Example 4.1 Capacitance of Metal Wire

Some global signals, such as clocks, are distributed all over the chip. The length of those wires can be substantial. For die sizes between 1 and 2 cm, wires can reach a length of 10 cm and have associated wire capacitances of substantial value. Consider an aluminum wire of 10 cm long and 1 µm wide, routed on the first Aluminum layer. We can compute the value of the total capacitance using the data presented in Table 4.2.

Area (parallel-plate) capacitance: (0.1 × 106_µm2_{)× 30 aF/µm}2_{= 3 pF}

Fringing capacitance: 2 × (0.1 × 106µm) × 40 aF/µm = 8 pF Total capacitance: 11 pF

Notice the factor 2 in the computation of the fringing capacitance, which takes the two sides of the wire into account.

Suppose now that a second wire is routed alongside the first one, separated by only the minimum allowed distance. From Table 4.3, we can determine that this wire will couple to the first with a capacitance equal to

Cinter =(0.1 × 10

6_µ

m) × 95 aF/µm = 9.5 pF which is almost as large as the total capacitance to ground!

A similar exercise shows that moving the wire to Al4 would reduce the capacitance to ground to 3.45 pF (0.65 pF area and 2.8 pF fringe), while the inter-wire capacitance would remain approximately the same at 8.5 pF.

4.3.2 Resistance

The resistance of a wire is proportional to its length L and inversely proportional to its cross-section A. The resistance of a rectangular conductor in the style of Figure 4.3 can be expressed as

(4.3) where the constant ρ is the resistivity of the material (in Ω-m). The resistivities of some commonly-used conductive materials are tabulated in Table 4.4. Aluminum is the inter- connect material most often used in integrated circuits because of its low cost and its com- patibility with the standard integrated-circuit fabrication process. Unfortunately, it has a large resistivity compared to materials such as Copper. With ever-increasing performance targets, this is rapidly becoming a liability and top-of-the-line processes are now increas- ingly using Copper as the conductor of choice.

Table 4.4 Resistivity of commonly-used conductors (at 20 C).

Material ρ (Ω-m) Silver (Ag) 1.6 × 10−8 R ρL A --- ρL HW --- = =

Since H is a constant for a given technology, Eq. (4.3) can be rewritten as follows,

R = R❑ (4.4)

with

R❑ = (4.5)

the sheet resistance of the material, having units of Ω/❑(pronounced as Ohm-per-square). This expresses that the resistance of a square conductor is independent of its absolute size, as is apparent from Eq. (4.4). To obtain the resistance of a wire, simply multiply the sheet resistance by its ratio (L/W).

Typical values of the sheet resistance of various interconnect materials are given in Table 4.5.

From this table, we conclude that Aluminum is the preferred material for the wiring of long interconnections. Polysilicon should only be used for local interconnect. Although the sheet resistance of the diffusion layer (n+, p+) is comparable to that of polysilicon, the use of dif- fusion wires should be avoided due to its large capacitance and the associated RCdelay.

Copper (Cu) 1.7 × 10−8 Gold (Au) 2.2 × 10−8 Aluminum (Al) 2.7 × 10−8 Tungsten (W) 5.5 × 10−8

Interconnect Resistance Design Data

Table 4.5 Sheet resistance values for a typical 0.25 µm CMOS process.

Material Sheet Resistance (Ω/❑) n- or p-well diffusion 1000 – 1500

n+_{, p}+ _{diffusion 50 – 150} n+_{, p}+ _{diffusion with silicide 3 – 5}

n+_{, p}+ _{polysilicon 150 – 200} n+_{, p}+ _{polysilicon with silicide 4 – 5}

Aluminum 0.05 – 0.1

Table 4.4 Resistivity of commonly-used conductors (at 20 C).

Material ρ (Ω-m) L W --- ρ H ----

Advanced processes also offer silicided polysilicon and diffusion layers. A silicide is a compound material formed using silicon and a refractory metal. This creates a highly conductive material that can withstand high-temperature process steps without melting. Examples of silicides are WSi_2, TiSi₂, PtSi₂, and TaSi. WSi₂, for instance, has a resistivity

ρ of 130 µΩ-cm, which is approximately eight times lower than polysilicon. The silicides are most often used in a configuration called a polycide, which is a simple layered combi- nation of polysilicon and a silicide. A typical polycide consists of a lower level of polysil- icon with an upper coating of silicide and combines the best properties of both materials—good adherence and coverage (from the poly) and high conductance (from the silicide). A MOSFET fabricated with a polycide gate is shown in Figure 4.8. The advan- tage of the silicided gate is a reduced gate resistance. Similarly, silicided source and drain regions reduce the source and drain resistance of the device.

Transitions between routing layers add extra resistance to a wire, called the contact resistance. The preferred routing strategy is thus to keep signal wires on a single layer whenever possible and to avoid excess contacts or via’s. It is possible to reduce the contact resistance by making the contact holes larger. Unfortunately, current tends to concentrate around the perimeter in a larger contact hole. This effect, called current crowding, puts a practical upper limit on the size of the contact. The following contact resistances (for min- imum-size contacts) are typical for a 0.25 µm process: 5-20 Ω for metal or polysilicon to n+, p+, and metal to polysilicon; 1-5 Ω for via’s (metal-to-metal contacts).

Example 4.2 Resistance of a Metal Wire

Consider again the aluminum wire of Example 4.2, which is 10 cm long and 1 µm wide, and is routed on the first Aluminum layer. Assuming a sheet resistance for Al1 of 0.075 Ω/❑, we can compute the total resistance of the wire

Rwire= 0.075 Ω/❑ × (0.1 × 10

6_µ

m) / (1 µm)= 7.5 kΩ

Implementing the wire in polysilicon with a sheet resistance of 175 Ω/❑ raises the overall resistance to 17.5 MΩ, which is clearly unacceptable. Silicided polysilicon with a sheet resis- tance of 4 Ω/❑ offers a better alternative, but still translates into a wire with a 400 kΩ resis- tance.

So far, we have considered the resistance of a semiconductor wire to be linear and constant. This is definitely the case for most semiconductor circuits. At very high frequen- cies however, an additional phenomenon — called the skin effect — comes into play such that the resistance becomes frequency-dependent. High-frequency currents tend to flow primarily on the surface of a conductor with the current density falling off exponentially

n+ n+

SiO₂ Polysilicon Silicide

with depth into the conductor. The skin depth δ is defined as the depth where the current falls off to a value of e-1 of its nominal value, and is given by

(4.6) with f the frequency of the signal and µ the permeability of the surrounding dielectric (typ- ically equal to the permeability of free space, or µ = 4π× 10-7 H/m). For Aluminum at 1 GHz, the skin depth is equal to 2.6 µm. The obvious question is now if this is something we should be concerned about when designing state-of-the-art digital circuits?

The effect can be approximated by assuming that the current flows uniformly in an outer shell of the conductor with thickness δ, as is illustrated in Figure 4.9 for a rectangu- lar wire. Assuming that the overall cross-section of the wire is now limited to approxi-

mately 2(W+H)δ, we obtain the following expression for the resistance (per unit length) at high frequencies (f > f_s):

(4.7) The increased resistance at higher frequencies may cause an extra attenuation — and hence distortion — of the signal being transmitted over the wire. To determine the on-set of the skin-effect, we can find the frequency f_s where the skin depth is equal to half the largest dimension (W or H) of the conductor. Below f_s the whole wire is conducting cur- rent, and the resistance is equal to (constant) low-frequency resistance of the wire. From Eq. (4.6), we find the value of f_s:

(4.8)

Example 4.3 Skin-effect and Aluminum wires

We determine the impact of the skin-effect on contemporary integrated circuits by analyz- ing an Aluminum wire with a resistivity of 2.7×10-8Ω-m, embedded in a SiO2 dielectric

with a permeability of 4π× 10-7 H/m. From Eq. (4.8), we find that the largest dimension of wire should be at least 5.2 µm for the effect to be noticeable at 1 GHz. This is confirmed