Interfacing Architecture Components

As already mentioned, the model components described so far communicate through well defined component interfaces9. There are three interface types, as depicted in Figure 3.1. Each of them goes with a particular protocol:

1. The push-pull protocols - the handshake protocols between processing units10_{as mas-}

ters and interface units11_{as slaves.}

2. The room-data protocol - the condition synchronization protocols between interface units when communicating data through FIFOs12_.

3. The claim-release protocol - the resource-sharing protocol between interface units when transferring data over the shared-resource13_.

One possible sequence involving all these protocols is illustrated in Figure 3.2. interface points among different architecture components are indicated by circled numbers; they cor- respond to the enumerations in Figure 3.1. To explain the protocol sequence illustrated in Figure 3.2 we use Dewey decimal numbers [68].

On the left hand side of the figure is illustrated a pull master-slave protocol. The pull protocol

pulls data into a processor component from the corresponding read-interface component. On

the right hand side of the figure, a push protocol illustrated. The push protocol pushes data from a processor component to the corresponding write-interface component. Both of the protocols consist of three parts. Firstly, the connections have to be opened: Dewey sequences 1.0 7→ 2.0 7→2.1 7→ 1.1for the pull-side and6.0 7→5.0 7→5.1 7→ 6.1for the push-side. Secondly, the real push or pull handshake protocols: sequences1.2 7→ 2.2 7→ 2.8 7→ 1.3 and 6.3 7→ 5.3 7→ 5.9 7→ 6.4, respectively. Thirdly, the connections have to be closed explicitly: sequences1.5 7→2.10for the pull-side and6.5 7→ 5.10for the push-side. Note that when looking into the write connection, data is moved from the processor component to a local memory of the write interface component prior to any handshake activity: the sequence6.27→5.2. On the contrary, when moving data from the read interface component to the processor component, the data is moved from a local memory of the read interface component to the processor component after all handshake activities are completed: The sequence2.97→1.4.

In the center of Figure 3.2, the condition synchronization protocols are illustrated. These are protocols that are convenient for the modeling of synchronization. The reader side (visible through the previously established pull connection) checks on the availability of data in a global memory buffer14_{. If the data is not in the memory buffer the reader side blocks until}

9_{The component interfaces are the interfaces from the component-based design point of view, unlike the router}

interface components we introduced in Section 3.3.2. Consequently, whenever we speak in terms of inter-component interfacing we refer to component interfaces, whereas when we speak in terms of the model description and assem- blies we refer to interface components or routers.

10_{See Section 3.3.1.} 11_{See Section 3.3.2.} 12_{See Section 3.3.4.} 13_{See Section 3.3.3.} 14_{See Section 3.3.4.}

PU RIF FIFO BUS WIF PU 2.0 1.1 3.0 4.0 3.2 1.0 1.2 1.3 1.4 1.5 2.1 2.2 2.3 2.5 2.7 2.9 2.8 2.10 3.1 3.3 3.5 4.2 4.3 5.0 5.1 5.2 5.3 5.4 5.5 5.7 5.6 3.4 5.8 5.9 5.10 6.0 6.1 6.2 6.3 6.4 6.5 close connection open connection 2.4 4.1 2.6 pull handshake wait data signal room bus claim bus release push handshake close connection open connection wait room signal data 1 1 2 3 2 3

Figure 3.2: The architecture model structure - sequence diagram describing the component interfaces.

it is notified that the data has arrived: Dewey sequence3.07→2.3. Similarly, the writer side (push connection) checks on the availability of room in the global memory buffer. If there is no available space in the memory buffer the writer side blocks until it is notified that sufficient space is available: The sequence3.1 7→5.4. In the particular case illustrated in Figure 3.2, neither of the two checks (data-to-read or room-to-write) give rise to blocking, which implies that the memory buffer (FIFO) has both enough data and room. When data is read from the memory buffer or when data is written to it, the signaling part of the synchronization protocol takes place: Dewey sequences2.27→ 3.3and5.87→ 3.5respectively. The former serves to update (atomically) the number of available data tokens. The latter serves to update (also atomically) the available space in the buffer. Note that in the case of Figure 3.2 data is transferred through the bus. Therefore, the load and the store activities (data transfers) are synchronized by the conditional synchronization protocol but they are only possible when the bus protocol is fulfilled.

Finally, there is a small part in Figure 3.2 where the resource sharing protocol is illustrated. This is a single bus protocol that allows only a single bus owner. For example, after the read interface has discovered that data tokens are available in the memory buffer, it claims the bus. When it has been given control over the bus, it loads the data from the global memory into the local memory of the read interface. After that, the read interface releases the bus, allowing a next bus request to take over the bus. The respective activities are depicted by the following Dewey sequence4.0 7→2.4; 3.27→2.5; 2.67→4.1(the semi-colon ’;’ sign forces the load data transfer between the bus claim and the bus release). On the contrary, the write interface side is blocked on the bus request - therefore it must first wait for the read interface to finish its data transfers. After that, it gains control, stores new data into the global memory buffer and releases the bus afterwards. This is illustrated by the following Dewey sequence:

4.27→5.5; 5.67→3.4; 5.77→4.3.