An interrupt is the method of accessing the MPU by a peripheral device. An interrupt is used to cause a temporary halt in the execution of a program. The MPU responds to the interrupt with an interrupt service routine, which is a short program or subroutine that instructs the MPU on how to handle the interrupt.
When the 8086 is executing a program, it can get interrupted because of one of the following.
1. Due to an interrupt getting activated. This is called as hardware interrupt.
2. Due to an exceptional happening during an instruction execution, such as division of a number by zero. This is generally termed as exceptions or Traps.
3. Due to the execution of an Interrupt instruction like "INT 21H". This is called a Software interrupt.
The action taken by the 8086 is similar for all the three cases, except for minor differences.
There are two basic types of interrupts, maskable and non-maskable. A nonmaskable interrupt requires an immediate response by the MPU. It is usually used for serious circumstances like power failure. A maskable interrupt is an interrupt that the MPU can ignore depending upon some predetermined condition defined by the status register. Interrupts are also prioritized to allow for the case when more than one interrupt needs to be serviced at the same time.
Hardware interrupts of 8086
In a microcomputer system whenever an I/O port wants to communicate with the microprocessor urgently, it interrupts the microprocessor. In such a case, the microprocessor completes the instruction it is presently executing. Then, it saves the address of the next instruction on the stack top. Then it branches to an Interrupt Service Subroutine (ISS), to service the interrupting I/O port. An ISS is also commonly called as an Interrupt Handler. After completing the ISS, the processor returns to the original program, making use of the return address that was saved on the stack top.
In 8086 there are two interrupt pins. They are NMI and INTR. NMI stands for
interrupt. This means, the 8086 knows where to branch to service the NMI request. If both NMI and INTR are activated at the same time, NMI will be serviced first.
In an 8086 system the first 1 K bytes memory from 00000H to 003FFH is set aside as a table for storing the starting addresses of interrupt service procedures. Since 4 bytes are required to store the CS and IP values for each interrupt service procedure, the table can store starting addresses for upto 256 interrupt procedures. The starting address of an Interrupt Service procedure stored in this table is often called as Interrupt Vector Table or the Interrupt Pointer Table.
Fig. 12 shows how the 256 interrupt pointers are arranged in the memory table.
The lowest five types are dedicated to specific interrupts such as the divide by zero interrupt and the non maskable interrupt. The next 27 interrupt types, from 5 to 31 are reserved by Intel for use in future microprocessors. The upper 224 interrupt types, from 32 to 255, are available to use for hardware and software interrupts.
Action taken by 8086 when NMI is activated
When NMI pin interrupts the 8086, a branch takes place to the ISS, whose interrupt type number is 2. The action taken is as follows:
1. Completes the current instruction that is in progress.
2. Push the Flag register values on to the stack.
3. Push the CS value and IP value of the return address on to the stack.
4. IP is loaded from contents of the word location 00008H.
5. CS is loaded from contents of next word location 0000AH.
6. Interrupt flag and trap Flag are reset to O.
Return from Interrupt Handler (IRET)
The execution of the IRET instruction results in POP from the stack top, the IP, CS and Flag registers. Thus return back to the interrupted program takes place. When the control is transferred back to the interrupted program, the register values are not the same it was before the occurrence of interrupt. To solve this problem, an ISS starts with saving register values on the stack. Finally, the register values are restored from the stack and a return to the interrupted program takes place using the IRET instruction.
Action taken by 8086 when INTR line is activated
Whenever an external signal activates the INTR pin, the microprocessor will be interrupted only if interrupts are enabled using set interrupt Flag instruction. If the interrupts are disabled using clear interrupt Flag instruction, the microprocessor will not get interrupted even if INTR is activated. That is, INTR can be masked.
INTR is a non vectored interrupt, which means, the 8086 does not know where to branch to service the interrupt. The 8086 has to be told by an external device like a Programmable Interrupt controller regarding the branch.
Whenever the INTR pin is activated by an I/O port, if Interrupts are enabled and NMI is not active at that time, the microprocessor finishes the current instruction that is being executed and gives out a ‘0’ on INTA pin twice. When INTA pin goes low for the first time, it asks the external device to get ready. In response to the second INTA the microprocessor receives the 8 bit, say N, from a programmable Interrupt controller. The action taken is as follows.
1. Complete the current instruction.
3. Flag register value, CS value of the return address & IP value of the return address are pushed on to the stack.
4. IP value is loaded from contents of word location N x 4.
5. CS is loaded from contents of the next word location.
6. Interrupt Flag and trap Flag are reset to 0.
At the end of the ISS, there will be an IRET instruction. This performs popping off from the stack top to IP, CS and Flag registers. Finally, the register values which are also saved on the stack at the start of ISS, are restored from the stack and a return to the interrupted program takes place using the IRET instruction.
Divide-by-zero interrupt - Type 0
The 8086 will automatically do a Type 0 interrupt if the result of a division operation is too large to fit in the destination register. For example, if we execute DIV BL, then AX will be divided by BL. The quotient will be stored in AL and the remainder in AH.
If AX content is 4060H and BL is 02H, then the quotient is 2030H. But the 8-bit AL register cannot hold this data. This results in automatic branching to an ISS. It is an internal interrupt, and the 8086 branches to an ISS whose interrupt Type number is 0.
Action taken by the 8086 when divide by zero error occurs is as follows.
1. Flag register value is pushed on to the stack.
2. CS value of the Return address and IP value of the Return address are pushed on to the stack.
3. IP is loaded from contents of word location 0x4 = 00000H.
4. CS loaded from contents of next word location, 00002H.
5. Interrupt Flag and trap Flag are reset to 0.
The action taken by the ISS could be to display a suitable error message on the CRT and then halt the proceedings. Or, it could be to set a bit in a memory location to indicate an error, and then return to the interrupted program using the IRET instruction.
Single-Step Interrupt - Type 1
When we tell a System to single- Step , it will execute one instruction and stop.
We can then examine the contents of the registers and memory locations. If they are correct, we can tell the system to go on and execute the next instruction. In other words, when in single-Step mode, a system will stop after it executes each instruction and wait for
further directions from the user. The 8086 trap flag and type 1 interrupt make it quite easy to implement a single-Step feature.
If the 8086 trap flag is set, the 8086 will automatically do a type 1 interrupt after executing each instruction. It is an internal interrupt caused by the completion of an instruction execution. It is useful for debugging a program.
The action taken by the 8086 when T flag is set to 1, and an instruction execution is completed is as follows.
1. Flag register values is pushed on to the stack.
2. CS value of the return address and IP value of the return address are pushed on to the stack.
3. IP is loaded from the contents of the word location, 1x4 = 00004H.
4. CS is loaded from contents of the next word location, 00006H.
5. Interrupt Flag and trap Flag are reset to 0.
The action taken by the ISS could be to display the contents of the various registers on the CRT and then return to the interrupted program using the IRET program.
Software interrupt Instructions
There are instructions in 8086 which cause an interrupt. They are 1. INT instructions with type number specified.
2. INT 3, Break Point Interrupt instruction.
3. INTO, Interrupt on overflow instruction.
These are instructions at the desired places in a program. When one of these instructions is executed a branch to an ISS takes place. Because their execution results in a branch to an ISS, they are called interrupts.
Software Interrupt instructions can be used to test the working of the various Interrupt handlers- For example, we can execute INTO instruction to execute type 0 ISS, with out really having to divide a number by 0. Similarly, we can execute INT 2 instruction to test NMI ISS.
INT-Interrupt Instruction with Type number Specified
The mnemonic for this is INT. It is a 2 byte instruction. The first byte provides the op-code and the second byte the Interrupt type number. Op-code for this instruction is
The execution of an INT instruction, say INTN, when N is the value in the range 00H to FFH, results in the following:
1. Flag register value is pushed on to the stack.
2. CS value of the Return address and IP value of the Return address are pushed on to the stack.
3. IP is loaded from the contents of the word location N x 4.
4. CS is loaded from the contents of the next word location.
5. Interrupt Flag and Trap Flag are reset to 0.
Thus a branch to the ISS take place. During the ISS, interrupts are disabled because the Interrupt flag is reset to 0.
At the end of the ISS, there will be an IRET instruction. Thus a return back to the interrupted program takes place with Flag registers unchanged.
INT 3-Break Point Interrupt Instruction
When a break point is inserted, the system executes the instructions upto the breakpoint, and then goes to the break point procedure. Unlike the single-Step feature which stops execution after each instruction, the breakpoint feature executes all the instructions upto the inserted breakpoint and then stops execution.
The mnemonic for the instruction is INT3. It is a 1 byte instruction Op-code for this is CCH.
The execution of INT3 instruction results in the following.
1. Flag register value is pushed on to the Stack.
2. CS value of the return address and IP value of the return address are pushed on to the Stack.
3. IP is loaded from the contents of the word location 3x4 = 0000CH.
4. CS is loaded from the contents of the next word location.
5. Interrupt Flag and Trap Flag are reset to 0.
Thus a branch to the ISS takes place. During the ISS, interrupts are disabled because Interrupt flag is reset to 0. At the end of the ISS, there will be an IRET instruction to return back to the interrupted program.
A break point interrupt service procedure usually saves all the register contents on the Stack. Depending upon the system, it may then send the register contents to the CRT display and wait for the next command from the user.
INTO - Interrupt on overflow instruction
The 8086 overflow flag, OF, will be set if the signed result of an arithmetic operation on two signed numbers is too large to be represented in the destination register or memory location. For example, if we add the bit signed number 01101100 and the 8-bit signed number 01010001, the signed result will be 10111101. This is correct if we add unsigned binary numbers, but it is not the correct signed result.
There are two ways to detect and respond to an overflow error in a program. One way is to put the jump if overflow instruction, JO, immediately after the arithmetic instruction. If the overflow flag is Set, execution will jump to the address specified in the JO instruction.
At this address an error routine may be put which respond to the overflow.
The second way is to put the INTO instruction immediately after the arithmetic instruction in the program. The mnemonic for the instruction is INTO. It is a 1 byte instruction. The op-code for this is CEH.
It is a conditional interrupt instruction. Only if the overflow flag is Set, a branch takes place to an interrupt handler whose interrupt type number is 4. If the overflow flag is reset, the execution continues with the next instruction.
The execution of INTO results in the following.
1. Flag register values are pushed on to the Stack.
2. CS value of the return address and IP value of the return address and IP value of the return address are pushed on to the stack.
3. IP is loaded from the contents of word location 4x4 = 00010H.
4. CS is loaded from the contents of next word location.
5. Interrupt flag and Trap flag are reset to 0.
Thus a branch to ISS takes place. During the ISS, interrupts are disabled. At the end of ISS, there will be an IRET instruction, returning back to the interrupted program.
Instructions in the ISS procedure perform the desired response to the error condition.
Priority of Interrupts
The internal interrupts which result is an error, like Divide by Zero error, as well as software interrupt instructions have the highest priority. Next priority is NMI. The next lower priority is assigned to INTR. The lowest priority is assigned to single Step interrupt.
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Chapter 7
I/O CONCEPT ( I/O MAPPED AND MEMORY MAPPED)