Materials characterization is fundamental to experimental condensed matter research. For accurate and precise models of the interrelation of material properties to be constructed, tested, improved and utilized the materials must be realized and tested in the physical world, not solely in computer simulations. Though useful for producing informed predictions, all material simulations are based on conceptual models which contain intrinsic assumptions and simplifications of the materials, which may or may not be sufficiently accurate for predicting the behaviour of the material under investigation. For example, the effect of such a large lattice mismatch and large difference in atomic radii between Ge and α-Sn and the meta-stability of their alloys is not accounted for in many common models used to predict the properties of semiconductors, such as the virtual crystal approximation, which can lead to significant errors in their predictions [5,51,102].
In this work, material characterization is necessary in order to understand the impact of growth parameters, such as growth temperature, on the produced material parameters, such as the alloy composition. Additionally materials characterization facilitates study of the interrelation between material parameters, such as the layer thickness and lattice strain. Additionally, in this work experiments are also undertaken to further our understanding of impact on the material to non-ambient temperatures, and for this the material properties prior to thermal treatments and post-treatments must be determined.
Crucial structural properties for thin layers of Ge1-xSnx alloys include the layer
thickness, the lattice strain state, the alloy composition, and the crystalline quality, including any lattice defects. The importance of each of structural aspects is highlighted by their effect on the properties of any devices, such as microelectronics or photonic, fabricated from such a material. In this work, materials characterization is focused on determining these properties in the investigated samples.
Electrical characterization is necessary to identify if material parameters and epitaxial structure produces desirable attributes for devices, such as a high charge carrier mobility. Additionally, electrical characterization is used to indicate the optimum device processes for particular applications, such as contact material to form an Ohmic contact. In this work electrical characterization is used to identify the relative quality of metal contacts on Ge1-xSnx epilayer samples.
No existing individual characterization technique is capable of accurately providing all of the necessary material information about a given sample, therefore a range of characterization methods are used in order to collect a range of data sufficiently detailed such that a comprehensive understanding of materials can be achieved.
Using multiple characterization methods which measure the same property additionally allows for greater confidence in the measured result.
Characterization techniques vary in what material or device properties they can determine, to what accuracy and from which region of the material. Additionally, some characterization methods are destructive; the investigated material is consumed for the measurement, which prevents the same piece of material being used for further investigation by other characterization techniques. Other experimental measurements are non-destructive, facilitating further investigations on the exact same section of the sample. The range of properties which need to be determined for the desired investigation and the availability of sample material dictate which techniques should be used. Additional constraints may also exist due to time and equipment limitations.
3.2 Chemical Vapour Deposition
All samples investigated in this work were grown at the University of Warwick. Materials growth was performed by my colleague and supervisor, Dr. Maksym Myronov. The RP-CVD reactor used for growth is the cold-wall ASM Epsilon 2000E, a photo of a comparable reactor is given in Figure 3-1. This tool is very well- established, and used throughout the world for both research purposes and commercial scale production of semiconductor thin films. The CVD configuration at the University of Warwick is optimised to grow on a single 100 mm wafers each growth cycle.
For Ge1-xSnx epitaxial layer growth, a digermane, Ge2H6, gas source was used as the
Ge precursor. Digermane is well established as a CVD precursor for the low temperature growth of both Ge and Ge1-xSnx layers [103]. Digermane is the optimal
Ge source as it facilitates higher growth rates at low temperatures than the lower order monogermane, GeH4, precursor; furthermore, digermane is lower cost and
more readily available than higher order germanes, such a trigermane, Ge3H8 [103–
105].
Tin-tetrachloride, SnCl4, was used as the tin source precursor, which is an established
CVD precursor used in tin-oxide and Sn1-xSex growth and more recently Ge1-xSnx
alloy growth [19,35,106,107]. SnCl4 is liquid at room temperature; therefore the
vapour is delivered to the CVD growth chamber by a bubbler system, with the Sn precursor flow controlled by liquid temperature and carrier gas flow rate. SnCl4 is
more readily available and cheaper to acquire than SnD4, the dominant alternative
successful Sn source for crystalline Ge1-xSnx CVD growth found in literature, and
SnCl4 does not have the issues of instability during storage experienced with SnD4.
Alternative Sn sources have been used in publications, such as Sn(CH3)4, but for
significantly different growth configurations with different target structures [108]. All Ge1-xSnx epitaxial layers studied in this work were produced with the growth
temperature in the range 250 °C to 350 °C. The substrate temperatures are Figure 3-1 A photo of the ASM Epsilon 2000, the same line of CVD
reactors to that used to produce the samples investigated in this work. Image modified from image originally obtained from ASM website.
determined by thermocouples, with heating provided by IR lamps. 350 °C is the maximum Ge1-xSnx growth temperature in the published literature, where direct
temperature measurements are used, with lower growth temperatures used to produce higher Sn fraction alloy epilayers.
Prior to growth, the 100 mm Si(001) substrate wafer is subject to standard chemical cleans, including a dilute HF rinse to remove the native oxide, both organic and inorganic contaminates, and leave a hydrogen-terminated growth surface. The Si substrate is then loaded into the CVD and transferred to the growth chamber via an automated handling system. Immediately prior to growth, the substrate undergoes a high temperature pre-epi at temperatures below 1000 °C bake to remove any residual SiO2.
Initially, a 600-800 nm thick strain relaxed Ge buffer is grown by a two-step growth method to provide a smooth and low defect density growth platform essential for the subsequent Ge1-xSnx growth [93]. The Ge buffer also serves to minimise the lattice
mismatch between the growth platform and the Ge1-xSnx alloy epilayer. The Ge1-xSnx
Figure 3-2 Photograph of two GeSn/Ge/Si wafers after being cleaved. The surface of both wafers is very smooth and reflective.
layer was then grown on the Ge platform, at a constant temperature. Figure 3-2 shows two 100 mm wafers after they have been cleaved.