Introduction to different transistor types

Combinational logic forms the core of most digital integrated circuits such as fast arithmetic units and controllers. The design requirements imposed on the logic circuitry can vary widely. Area is often the prime concern, as it has direct impact on cost. In many state-of-the-heart designs, speed tends to be the dominating requirement. Contemporary microprocessors are excellent examples of designs in this class. For other applications, minimizing the power consumption is crucial, as in the design of portable applications such as mobile telephones. These different design requirements generally translate into the use of different circuit styles, or even different manufacturing technologies.

The static CMOS has excellent properties in many areas: low sensitivity to noise and process variations, excellent speed, and low power consumption. Most of those properties are carried over to more static CMOS gates such as NAND gates with three or more inputs become large and slow. Other design styles like complementary, the ratioed and the pass transistor logic styles have been devised to address this issue, all of which belong to the class of static circuits.

4.1.1 Complementary CMOS

A static CMOS gate is a combination of two networks, called the pull-up network (PUN) and the pull-down network (PDN). The PUN consists solely of PMOS transistors and provides a conditional connection to Vdd. The PDN potentially connects the output to Vss and contains only NMOS devices. The PUN and PDN networks should be designed so that, whatever the value of the inputs, one and only one of the networks is conducting in steady state. In this way, a path always exists between Vdd and the output, realizing a high output (one) or alternatively, between Vss

and output for a low output (zero).

Properties of complementary CMOS

Complementary CMOS gates inherit all the nice properties like high noise margin, no static power consumption, as there is never a direct path between Vdd and Vss in steady state mode and comparable rise and fall times.

The complementary gate is inverting (implementing functions such as NAND, NOR & XNOR). Implementing a non inverting Boolean function (such as AND, OR, XOR) in one stage is not possible and requires the addition of an extra inverter stage.

4.1.2 Pseudo NMOS

A grounded PMOS device presents an even better load. This configuration which is called pseudo-NMOS because it resembles the depletion NMOS load, is superior to the other approach. First of all, the PMOS transistor does not experience anybody effect as its Vsb is constant and equal to 0. Secondly, the PMOS device is driven by a Vgs equal to –Vdd, resulting in a higher load-current level for similarly sized devices.

Figure 4.1 Pseudo NMOS

An important disadvantage is that it consumes static power when the output is low, because a direct path exists between Vdd and ground through the load and device drivers.

The grounded PMOS load is a good imitation of an ideal current-source load.

For a certain circuit configurations, some simple modifications can further improve

either the speed or the power consumption. The following approach allows to completely eliminating the static current.

4.1.3 Differential cascade voltage switch logic (DCVSL)

Let us consider that the complement of each signal is always available. This requires each gate to generate both polarities of the output signal. Such a gate, called Differential Cascade Voltage Switch Logic (DCVSL) is presented. The PDN1 &

PDN2 are complementary, and implement the required logic function and its inverse.

Assume now that, for a given set of inputs, PDN1 conducts while PDN2 does not.

Node out is pulled down. This turns on the load transistor M2, pulling up out’. This in turn cuts off load transistor M1. The gate is clearly free of static current paths as only PDN1 & M2 are conducting.

Figure 4.2 DCVSL logic gate Basic Principle

Figure 4.3 XOR-XNOR gates

The availability of complementary signals eliminates extra inverter stages. An example in the circuit implements a two input XOR and XNOR gate. The transistor connected to the A-inputs are shared between the two PDNs. DCVSL has, for instance, been used for the implementation of fast error-correcting logic in memories.

The DCVSL gate has the speed advantage; the reduction of the parasitic capacitances at the output nodes produces a faster response. At the same time the static power consumption is eliminated. This comes at the expense of extra area, as each gate requires two pull-down networks.

4.1.4 Pass transistor logic

This is another promising approach to implement complex logic by realizing it as a logical network of switches or pass transistors. The pass transistor approach has the advantage of being simple and fast. Complex CMOS combinational logic is implemented with a minimal number of transistors. This reduces the parasitic capacitances and results in fast circuits. The static and transient performance of such a structure strongly depends upon the availability of a high-quality switch with low parasitic capacitance and resistance. Although the MOS transistor in itself is a switch of reasonable performance, some deficiencies will become apparent. Pass transistor logic networks are, therefore, often constructed from bidirectional transmission gates (pass gates). These gates are composed of an NMOS transistor and a PMOS device in a parallel arrangement. The pass transistor acts as a bidirectional switch controlled by the gate signal C. When C=1, both MOSFETs are on, allowing the signal to pass through the gate i.e., A=B if C=1. On the other hand, C=0 places both transistors in cutoff, creating an open circuit between nodes A and B.

Figure 4.4 Pass transistor logic

Although the pass transistor possesses some excellent properties, such as an almost constant resistance and no threshold loss, it has the disadvantage that it requires both an NMOS and a PMOS transistor, which have to be located in different wells. This reduces the layout efficiency of the design. Also, the control signal has to be presented in both the polarities, which once again has a negative influence on the layout density. Furthermore, the parallel connection of PMOS and NMOS results in increased node capacitances and reduced performance. It would therefore be advantageous if we could implement transmission gate using NMOS transistor only.

Unfortunately, NMOS only pass transistors are subject to voltage loss. This is not a problem if the voltage levels are subsequently restored by a complementary CMOS inverter. Such a circuit suffers from two major drawbacks: reduced noise margin, due to threshold voltage drop and static power consumption. Several techniques have been proposed to get around this problem.

4.1.5 Transmission Gate logic

Transmission gate logic includes at least two field-effect transistor elements used as pass transistors, each having a channel of conductivity type opposite that of the other (i.e., complementary FET’s).

Transmission gate is switching element which switches the input to the output according to the gate input. Transmission gate is parallel connection of n-transistor, which is good at pass logic one and p-transistor which is good at pass logic zero. The basic arrangement of transmission gate is shown in figure 4.5.

Figure 4.5 A simple Transmission gate