Intel XScale ® Core 3
3.10 Test Features
3.10.1 IXP2800 Network Processor Endianness
Endianness defines the way bytes are addressed within a word. A little-endian system is one in which byte 0 is the least significant byte (LSB) in the word and byte 3 is the most significant byte (MSB). A big-endian system is one in which byte 0 is the MSB and byte 3 is the LSB. For example, the value of 0x12345678 at address 0x0 in a 32-bit little-endian system looks like this:
The same value stored in a big-endian system is shown in Table 44:
Bits within a byte are always in little-endian order. The least significant bit resides at bit location 0 and the most significant bit resides at bit location 7 (7:0).
The following conventions are used in this document:
Endianness for the IXP2800 network processor can be divided into three major categories:
•
Read and write transactions initiated by the Intel XScale® core:— Reads initiated by the Intel XScale® core
— Writes initiated by the Intel XScale® core
•
SRAM and DRAM access:— 64-bit Data transfer between DRAM and the Intel XScale® core
— Byte, word, or longword transfer between SRAM/DRAM and the Intel XScale® core
— Data transfer between SRAM/DRAM and PCI
— Microengine-initiated access to SRAM and DRAM
•
PCI Accesses— Intel XScale® core generated reads/writes to PCI in memory space
— Intel XScale® core generated read/write of external/internal PCI configuration registers Table 43. Little-Endian Encoding
Address/Byte
Lane 0x0/ByteLane 3 0x0/ByteLane 2 0x0/ByteLane 1 0x0/ByteLane 0
Byte Value 0x12 0x34 0x56 0x78
Table 44. Big-Endian Encoding
Address/Byte
Lane 0x0/ByteLane 3 0x0/ByteLane 2 0x0/ByteLane 1 0x0/ByteLane 0
Byte Value 0x78 0x56 0x34 0x12
1 Byte: 8-bit data 1 Word: 16-bit data 1 Longword: 32-bit data Longword Little-Endian
Format (LWLE) 32-bit data (0x12345678) arranged as {12 34 56 78}
64-bit data 0x12345678 9ABCDE56 arranged as {12 34 56 78 9A BC DE 56}
Longword Big-Endian format
(LWBE): 32-bit data (0x12345678) arranged as {78 56 34 12}
64-bit data 0x12345678 9ABCDE56 arranged as {78 56 34 12, 56 DE BC 9A}
3.10.1.1 Read and Write Transactions Initiated by the Intel XScale
®Core
The Intel XScale® core may be used in either a little-endian or big-endian configuration. The configuration affects the entire system in which the Intel XScale® core microarchitecture exists.
Software and hardware must agree on the byte ordering to be used. In software, a system’s byte order is configured with CP15 register 1, the control register. Bit 7 of this register, the B bit, informs the processor of the byte order in use by the system. Note that this bit takes effect even if the MMU is not otherwise in use or enabled. The state of this bit is reflected in the cbiBigEndian signal.
Although it is the responsibility of system hardware to assign correct byte lanes to each byte field in the data bus, in the IXP2800 network processor, it is left to the software to interpret byte lanes in accordance with the endianness of the system. As shown in Figure 24, system byte lanes 0 – 3 are connected directly to the Intel XScale® core byte lanes 0 – 3. This means that byte lane 0 (M[7:0]) of the system is connected to byte lane 0 (X[7:0]) of the Intel XScale® core, byte lane 1 (M[15:8]) of the system is connected to byte lane 1 (X[15:8]) of the Intel XScale® core, etc.
Interface operation of the Intel XScale® core and the rest of the IXP2800 network processor can be divided into two parts:
•
Intel XScale® core reading from the IXP2800 network processor•
Intel XScale® core writing to the IXP2800 network processor 3.10.1.1.1 Reads Initiated by the Intel XScale® CoreIntel XScale® core reads can be one of the following three types:
•
Byte read•
16-bits (word) read•
32-bits (longword) read Byte ReadWhen reading a byte, the Intel XScale® core generates the byte_enable that corresponds to the proper byte lane as defined by the endianness setting. Table 45 summarizes byte-enable generation for this mode.
The 4-to-1 multiplexer steers the byte read into the byte lane 0 location of the read register inside the Intel XScale® core. Select signals for the multiplexer are generated based on endian setting and ByteEnable generated by the Intel XScale® core as defined in Figure 24.
Table 45. Byte-Enable Generation by the Intel XScale® Core for Byte Transfers in Little- and Big-Endian Systems
Byte Number to be Read
Byte-Enables for Little-Endian System Byte-Enables for Big-Endian System X_BE[0] X_BE[1] X_BE[2] X_BE[3] X_BE[0] X_BE[1] X_BE[2] X_BE[3]
Byte 0 1 0 0 0 0 0 0 1
Byte 1 0 1 0 0 0 0 1 0
Byte 2 0 0 1 0 0 1 0 0
Byte 3 0 0 0 1 1 0 0 0
16-Bit (Word) Read
When reading a word, the Intel XScale® core generates the byte_enable that corresponds to the proper byte lane as defined by the endianness setting. Figure 25 summarizes byte enable generation for this mode.
The 4-to-1 multiplexer steers byte lane 0 or byte lane 2 into the byte 0 location of the read register inside the Intel XScale® core. The 2-to-1 multiplexer steers byte lane 1 or byte lane 3 into the byte 1 location of the read register inside the Intel XScale® core. The Intel XScale® core does not allow word access to an odd-byte address. Select signals for the multiplexer are generated based on endian setting and ByteEnable generated by the Intel XScale® core, as defined in Figure 24.
Table 46 summarizes byte-enable generation for this mode.
Figure 24. Byte Steering for Read and Byte-Enable Generation by the Intel XScale® Core
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Intel XScale® Core
Intel® IXP2800 Core Gasket
Notes: For 32-bit Operation S0[3:0] = 0001; S1[1:0] = 01 Otherwise: S0[3:0] = X_BE[3:0]; S1[1:0] = X_BE[1:2]
32-Bit (Longword) Read
32-bit (longword) reads are independent of endianness. Byte lane 0 from the Intel XScale® core’s data bus gets into the byte 0 location of the read register inside the Intel XScale® core, byte lane 1 from the Intel XScale® core’s data bus gets into the byte 1 location of the read register inside the Intel XScale® core, etc. The software determines byte location, based on the endian setting.
3.10.1.1.2 The Intel XScale® Core Writing to the IXP2800 Network Processor
Writes by the Intel XScale® core can also be divided into the following three categories:
•
Byte Write•
Word Write (16 bits)•
Longword write (32 bits) Byte WriteWhen the Intel XScale® core writes a single byte to external memory, it puts the byte in the byte lane where it intends to write it, along with the byte enable for that byte turned ON, based on the endian setting of the system. Intel XScale® core register bits [7:0] always contain the byte to be written, regardless of the B-bit setting.
For example, if the Intel XScale® core wants to write to byte 0 in the little-endian system, it puts the byte in byte lane 0 and turns X_BE[0] to ON. If the system is big-endian, the Intel XScale® core puts byte 0 in byte lane 3 and turns X_BE[3] to ON. Other possible combinations of byte lanes and byte enables are shown in the Table 47. Byte lanes other than the one currently being driven by the Intel XScale® core, contain undefined data.
Table 46. Byte-Enable Generation by the Intel XScale® Core for 16-Bit Data Transfers in Little-and Big-Endian Systems
Word to be Read
Byte-Enables for Little-Endian System Byte-Enables for Big-Endian System X_BE[0] X_BE[1] X_BE[2] X_BE[3] X_BE[0] X_BE[1] X_BE[2] X_BE[3]
Byte 0,
Byte 1 1 1 0 0 0 0 1 1
Byte 2,
Byte 3 0 0 1 1 1 1 0 0
Table 47. Byte-Enable Generation by the Intel XScale® Core for Byte Writes in Little- and Big-Endian Systems
Byte Number to be Written
Byte-Enables for Little-Endian Systems Byte-Enables for Big-Endian Systems X_BE[0] X_BE[1] X_BE[2] X_BE[3] X_BE[0] X_BE[1] X_BE[2] X_BE[3]
Byte 0 1 0 0 0 0 0 0 1
Byte 1 0 1 0 0 0 0 1 0
Byte 2 0 0 1 0 0 1 0 0
Byte 3 0 0 0 1 1 0 0 0
Word Write (16-Bits Write)
When the Intel XScale® core writes a 16-bit word to external memory, it puts the bytes in the byte lanes where it intends to write them along with the byte enables for those bytes turned ON based on the endian setting of the system. The Intel XScale® core does not allow a word write on an odd-byte address. The Intel XScale® core register bits [15:0] always contain the word to be written regardless of the B-bit setting.
For example, if the Intel XScale® core wants to write one word to a little-endian system at address 0x0002, it will copy byte 0 to byte lane 2 and byte 1 to byte lane 3 along with X_BE[2] and X_BE[3] turned ON. If the Intel XScale® core wants to write one word to a big-endian system at address 0x0002, it will copy byte 0 to byte lane 0 and byte 1 to byte lane 1 along with X_BE[0] and X_BE[1] turned ON. Table 48 shows other possible combinations of byte lanes and byte enables.
Byte lanes other than those currently driven by the Intel XScale® core contain undefined data.
Longword (32-Bits) Write
The longword to be written is put on the Intel XScale® core’s data bus with byte 0 on X[7:0], byte 1 on X[15:8], byte 2 on X[23:16], and byte 4 on X[31:24] (see Figure 25). All of the byte enables are turned ON. A 32-bit longword write (0x12345678) by the Intel XScale® core to address 0x0000 regardless of endianness, causes byte 0 (0x78) to be written to address 0x0000, byte 1 (0x56) to address 0x0001, byte 2 (0x34) to address 0x0002, and byte 3 (0x12) to address 0x0003.
Table 48. Byte-Enable Generation by the Intel XScale® Core for Word Writes in Little- and Big-Endian Systems
Word to be Written
Byte-Enables for Little-Endian Systems Byte-Enables for Big-Endian Systems X_BE[0] X_BE[1] X_BE[2] X_BE[3] X_BE[0] X_BE[1] X_BE[2] X_BE[3]
Byte 0,
Byte 1 1 1 0 0 0 0 1 1
Byte 2,
Byte 3 0 0 1 1 1 1 0 0
Figure 25. Intel XScale® Core-Initiated Write to the IXP2800 Network Processor
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Write M[7:0]
M[15:8]
M[23:16]
M[31:24]
X [7:0]
X_BE [0]
X [15:8]
X [23:18]
X [31:24]
Byte Write by Intel XScale® Core
Intel® IXP2800 Core Gasket
X_BE [1]
X_BE [2]
X_BE [3]