OF EXTREME ENVIRONMENT ELECTRONICS
5.4 Simulations and Results
5.4.1 Layout-level Simulations
Spice netlists were extracted for each of the individual modules and the top-level design. These netlists were then simulated using HSpice for simple test cases as complete tests are
exorbitantly time-consuming. Simulation snapshots for the individual modules are shown in Figure 5.10 through Figure 5.13.
121
Figure 5.11. Layout-level simulation of the system monitor module (in a monitoring cycle)
Figure 5.13. Layout level simulation of the internal fitness evaluation module (containing FEM_Controller, excitation, and slew rate modules)
5.5 Summary
Evolvable analog electronics are useful in many space applications. In this work, a digital framework is proposed for the realization of self reconfigurable electronics that performs
autonomous monitoring and compensation of analog electronics operating under extreme environments. The proposed system has been implemented as a digital ASIC to reduce the form factor of the overall system and is also scalable with respect to the number of fitness functions.
123
CHAPTER 6 CONCLUSIONS
The complexity of designing hardware systems has increased significantly with
technological advances. Irrespective of the choice of hardware implementation, technology scaling has affected the design process by increasing the complexity of the designs that can be
implemented on a single chip, and by introducing new challenges in the form of interconnect, thermal, and reliability issues. Effective optimization techniques are required in all the stages of the hardware design cycle. Genetic algorithms have been shown to be a robust search mechanism in a wide variety of problem domains. In this dissertation, it has been shown that genetic
algorithms can be used successfully to address the optimization needs of the hardware design process. Specifically, this dissertation has used genetic algorithm based optimizers to address the following hardware design problems:
Layout optimization of VLSI ASICs – A genetic algorithm based multi-objective floorplanner has been developed for solving the outline-free macro-cell based ASIC design problem. The proposed floorplanner outperforms all existing floorplanners that perform simultaneous optimization of floorplan area and wirelength.
Reconfigurable Hardware Design of Optimization Applications – A customizable FPGA IP core of a general purpose genetic algorithm has been developed to alleviate the design of hardware applications that need an effective optimization engine.
Design, Monitoring and Performance Compensation of Extreme Environment Electronics – A digital framework has been developed for the evolutionary design of analog
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electronics. The proposed digital framework also performs autonomous monitoring and automatic performance compensation of the evolved analog electronics when operating in extreme environments.
125 REFERENCES
[1] International Technology Roadmap for Semiconductors. 2007.
[2] J. H. Holland, Adaptation in Natural and Artificial Systems, University of Michigan Press, Ann Arbor, 1975.
[3] David E. Goldberg, Genetic Algorithms in Search, Optimization, and Machine Learning. 1989: Addison-Wesley Publishing Company, Inc.
[4] Lawrence Davis, Handbook of Genetic Algorithms, 1991.
[5] R. Haupt and S. E. Haupt, Practical Genetic Algorithms, 2ed, John Wiley and Sons, Inc., 2004.
[6] J. J. Grefenstette, R. Gopal, B. J. Rosmaita, and D. Van Gucht, “Genetic Algorithms for
the Traveling Salesman Problem,” Proceedings of the 1st International Conference on
Genetic Algorithms, pp. 160-168, 1985.
[7] M. Vellasco, R. Zebulum, and M. Pacheco, “Evolutionary Electronics: Automatic Design
of Electronic Circuits and Systems by Genetic Algorithms,” 1st edition, CRC Press, 2001. [8] G. Rudolph, “Evolutionary Search for Minimal Elements in Partially Ordered Finite
Sets”, Proceedings of the 7th International Conference on Evolutionary Programming, pp.
345-353, 1998.
[9] G. Rudolph, “On a multi-objective evolutionary algorithm and its convergence to the
Pareto set”, IEEE International Conference on Evolutionary Computation, pp. 511-516,
1998.
[10] Kalyanmoy Deb, Multi-Objective Optimization using Evolutionary Algorithms. 1st edition, John Wiley & Sons, Ltd, 2001.
[11] J. D. Schaffer, “Multiple Objective Optimization with Vector Evaluated Genetic
Algorithms”, Proceedings of the 1st International Conference on Genetic Algorithms,
1985.
[12] N. Srinivas, and K. Deb, “Multiobjective Optimization Using Nondominated Sorting in
Genetic Algorithms”, IEEE Transactions on Evolutionary Computation, vol: 2, pp. 221-
248, 1994.
[13] J. Horn, N. Nafpliotis, and D.E. Goldberg, “A niched Pareto genetic algorithm for
multiobjective optimization”, Proceedings of the First IEEE Conference on Evolutionary
[14] E. Zitzler, and L. Thiele, “Multiobjective evolutionary algorithms: a comparative case
study and the strength Pareto approach”, IEEE Transactions on Evolutionary
Computation, vol. 3(4): pp. 257-271, 1999.
[15] K. Deb, A. Pratap, S. Agarwal, and T. Meyarivan, “A fast and elitist multiobjective
genetic algorithm: NSGA-II”, IEEE Transactions on Evolutionary Computation, vol. 6(2):
pp. 182-197, 2002.
[16] H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, “VLSI module placement based on
rectangle-packing by the sequence-pair”, IEEE Transactions on Computer-Aided Design
of Integrated Circuits and Systems, vol: 15(12), pp. 1518-1524, 1996.
[17] X. Tang, R. Tian, and D.F. Wong, “Fast evaluation of Sequence Pair in block placement
by longest common subsequence computation”, IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems, vol: 20(12), pp. 1406-1413, 2001.
[18] G. Pei-Ning, C. Chung-Kuan, and T. Yoshimura, “An O-tree representation of non-slicing
floorplan and its applications”, in Design Automation Conference, 1999.
[19] J.-M. Lin, and Y.-W. Chang, “TCG: A Transitive Closure Graph-Based Representation
for Non-Slicing Floorplans”, in Design Automation Conference, 2001.
[20] J.-M. Lin, and Y.-W. Chang, “TCG-S: orthogonal coupling of P*-admissible
representations for general floorplans”, IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, vol: 23(6), pp. 968-980, 2004.
[21] S. N. Adya and I. L. Markov, "Fixed-outline Floorplanning: Enabling Hierarchical
Design", IEEE Trans. on VLSI Systems, vol: 11(6), pp. 1120-1135, December 2003.
[22] H. H. Chan, S.N. Adya, and I.L. Markov, “Are floorplan representations important in
digital design?,” Proceedings of the 2005 international symposium on physical design, pp.
129-136, 2005.
[23] K. Jae-Gon, and K. Yeong-Dae, “A linear programming-based algorithm for
floorplanning in VLSI design,” IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, vol: 22(5), pp. 584-592, 2003.
[24] S. Dong, X. Hong, Y. Wu, Y. Lin, and J. Gu, “Module placement based on quadratic
programming and rectangle packing using less flexibility first principle,” in International
Symposium on Circuits and System, vol:5, pp. V-61-V-64, 2004.
[25] J.P. Cohoon, and W.D. Paris, “Genetic Placement”, IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, vol: 6(6), pp. 956-964, 1987.
[26] J.P. Cohoon, S. Hegde, W. Martin, and D. Richards, “Distributed genetic algorithms for
the floorplan design problem,” IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, vol: 10(4), pp. 483-492, 1991.
[27] H. Esbensen, “A genetic algorithm for macro cell placement,” Proceedings of the European Design Automation conference, pp. 52-57, 1992.
127
[28] K. Hatta, S. Wakabayashi, and T. Koide, “Solving the rectangular packing problem by an
adaptive GA based on sequence-pair”, in Proceedings of ASPDAC, pp. 181-184, 1999.
[29] S. Nakaya, T. Koide, and S. Wakabayashi, “An adaptive genetic algorithm for VLSI
floorplanning based on sequence-pair,” IEEE International Symposium on Circuits and
Systems, pp. 65-68, 2000.
[30] L. Chang-Tzu, C. De-Sheng, and W. Yi-Wen, “An efficient genetic algorithm for slicing
floorplan area optimization,” IEEE International Symposium on Circuits and Systems,
2002.
[31] C. L. Valenzuela, and P. Y. Wang, “VLSI placement and area optimization using a
genetic algorithm to breed normalized postfix expressions,” IEEE Transactions on
Evolutionary Computation, vol: 6(4), pp. 390-401, 2002.
[32] Andrew Kahng, "Classical Floorplanning Harmful?," Proceedings of ACM International Symposium on Physical Design, pp. 207-213, April 2000.
[33] Yan Feng, Dinesh P. Mehta, and Hannah Yang, “Constrained "Modern" Floorplanning,” Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA.
[34] Tung-Chieh Chen, and Yao-Wen Chang, “Modern floorplanning based on fast simulated
annealing,” Proceedings of the 2005 international symposium on Physical design, April
03-06, 2005, San Francisco, California, USA.
[35] Yong Zhan, Yan Feng, and Sachin S. Sapatnekar, “A fixed-die floorplanning algorithm
using an analytical approach,” Proceedings of the 2006 conference on Asia South Pacific
design automation, January 24-27, 2006, Yokohama, Japan.
[36] H. Esbensen and E. Kuh, “A performance-driven IC/MCM placement algorithm featuring
explicit design space exploration,” ACM Transactions on Design Automation of
Electronic Systems, vol:2(1), pp. 62-80, January 1997.
[37] R. P. Dick, and N. K. Jha, "MOGAC: a multiobjective genetic algorithm for the co-
synthesis of hardware-software embedded systems," Digest of Technical Papers,
IEEE/ACM International Conference on Computer-Aided Design, pp.522-529, 1997. [38] D. Chatterjee and T.W. Manikas, “Power-Density Aware Floorplanning for Reducing
Maximum On-Chip Temperature," Proceedings of 18th IASTED International Conference
on Modelling and Simulation (ICMS), pp. 319-324, 2007.
[39] D. Chatterjee, T.W. Manikas, and I. Markov, “COOLER- A Fast Multiobjective Fixed-
outline Thermal Floorplanner," Proceedings of the 3rd annual Austin Conf. on Integrated
Systems & Circuits (ACISC-08), May 2008.
[40] Xin Hao, and F. Brewer, "Wirelength optimization by optimal block orientation," IEEE/ACM International Conference on Computer-Aided Design, pp. 64-70, 2005. [41] S. D. Scott, A. Samal, and S. Seth, “HGA: a hardware-based genetic algorithm,” ACM
[42] M. Tommiska, and J. Vuori, “Implementation of genetic algorithms with programmable
logic devices,” Proceedings of 2NWGA, pp. 71-78, 1996.
[43] B. Shackleford, G. Snider, R. Carter, E. Okushi, M. Yasuda, K. Seo, and H. Yasuura, “A
High-Performance, Pipelined, FPGA-based Genetic Algorithm Machine,” Genetic
Algorithms and Evolvable Machines, vol: 2, pp. 33-60, 2001.
[44] N. Yoshida, and T. Yasuoka, “Multi-GAP: Parallel and Genetic Algorithms in VLSI,” Proceedings of SMC, pp. 571-576, 1999.
[45] W. Tang, and L. Yip, “Hardware Implementation of Genetic Algorithms using FPGA,” Proceedings of the 47th MWCAS, pp. 549-552, 2004.
[46] C. Aporntewan, and P. Chongstitvatana, “A hardware implementation of the compact
genetic algorithm,” Proceedings of the Congress on Evolutionary Computation, pp. 624 -
629, 2001.
[47] P. Graham, and B. E. Nelson, “Genetic algorithms in software and hardware – a
performance analysis of workstation and custom machine implementation”, IEEE
Symposium on FPGAs for Custom Computing Machines, pp. 216-225, 1996. [48] M. S. Jelodar, M. Kamal, S. Fakhraie, and M. Ahmadabadi, “SOPC-Based Parallel
Genetic Algorithm in Evolutionary Computation,” IEEE Congress on CEC, 2006.
[49] N. Nedjah, and L. De Macedo Mourelle, “Massively parallel hardware architecture for
genetic algorithms,” Proceedings of 8th Euromicro Conference on Digital System Design,
2005.
[50] S. Wakabayashi, T. Koide, K. Hatta, Y. Nakayama, M. Goto, and N. Toshine, “GAA: a
VLSI genetic algorithm accelerator with on-the-fly adaptation of crossover operators,”
Proceedings of the IEEE Intl. Symposium on Circuits and Systems, pp. 268-271, 1998. [51] P. -Y. Chen, R-D. Chen, Y-P. Chang, L-S. Shieh, and H. Maliki, “Hardware
Implementation for a Genetic Algorithm,” IEEE Transactions on Instrumentation and
Measurement, vol: 57(4), pp. 699-705, April 2008.
[52] K. Sai Mohan, and B. Nowrouzian, “A Diversity Controlled Genetic Algorithm for
Optimization of FRM Digital Filters over DBNS Multiplier Coefficient Space,” IEEE
International Symposium on Circuits and Systems, 2007.
[53] J. Holleman, B. Otis, S. Bridges, A. Mitros, and C. Diorio, “A 2.92 μW hardware random
number generator,” Proceedings of IEEE ESSCIRC, 2006.
[54] M. Meysenburg, “The effect of pseudo-random number generation quality on the
performance of a simple genetic algorithm,” Master‟s Thesis, University of Idaho, 1997.
[55] M. Meysenburg, and J. A. Foster, “Randomness and GA performance, revisited,” Proceedings of the Genetic and Evolutionary Computation Conference, vol: 1, pp. 425- 432, 1999.
129
[56] E. Cantú-Paz, “On random numbers and the performance of Genetic Algorithms,” Proceedings of the Genetic and Evolutionary Computation Conference, pp. 311-318, July 9 - 13, 2002.
[57] Simson Garfinkel, and Gene Spafford, “Practical UNIX and Internet Security,” Second Edition, O‟Reilly books, April 1996.
[58] U. Elsner, “Influence of random number generators on graph partitioning algorithms,” Electronic Transactions on Numerical Analysis, vol: 21, pp. 125-133, 2005.
[59] H. De Garis, “Evolvable Hardware: Genetic Programming of a Darwin Machine,” Intl. conference on Artificial Neural Networks and Genetic Algorithms, Spinger Verlag, 1993. [60] I.Kajitani, T. Hoshino, D. Nishikawa, H. Yokoi, S. Nakaya, T. Yamauchi, T. Inuo, N.
Kajihara, M. Iwata, D. Keymeulen, and T. Higuchi, “A gate-level EHW chip:
Implementing GA operations and reconfigurable hardware on a single LSI,” Proceedings
of International conference on Evolvable Systems: From Biology to Hardware, ICES 1998.
[61] N. J. Macias, “The PIG paradigm: the design and use of a massively parallel fine grained
self-reconfigurable infinitely scalable architecture,” Proceedings of the First NASA/DoD
Workshop on Evolvable Hardware, pp. 175-180, 1999.
[62] A. Stoica, D. Keymeulen, D. Vu, R. Zebulum, I. Ferguson, T. Daud, T. Arsian, and G. Xin, "Evolutionary recovery of electronic circuits from radiation induced faults," Congress on Evolutionary Computation, vol: 2, pp. 1786-1793, 2004.
[63] J. Langeheine, K. Meier, J. Schemmel, and M. Trefzer. “Intrinsic evolution of digital-to-
analog converters using a CMOS FPTA chip,” Proceedings of NASA/DoD Conference on
Evolvable Hardware, pp. 18-25, 2004.
[64] V. Baumgarte, F. May, A Nückel, M. Vorbach, and M. Weinhardt, “PACT XPP - A self-
reconfigurable Data Processing Architecture,” presented at ERSA'01, Las Vegas, NV,
CSREA Press, 2001.
[65] C. Lambert, T. Kalganova, and E. Stomeo, “FPGA-based systems for evolvable
hardware,” Proceedings of World Academy of Science, Engineering and Technology, vol:
12, pp. 123-129, March 2006.
[66] E. M. Sentovich, K. J. Singh, C. Moon, H. Savoj, R. K. Brayton, and A. Sangiovanni- Vincentelli, "Sequential circuit design using synthesis and optimization," Proceedings of IEEE International Conference on Computer Design, pp. 328-333, 1992.
[67] A. Stoica, A. Fukunaga, K. Hayworth, and C. Salazar-Lazaro, “Evolvable Hardware for
Space Applications,” ICES, LNCS 1478, pp. 166-173, 1998.
[68] A. Stoica, D. Keymeulen, M. Mojarradi, R. Zebulum, and T. Daud, "Progress in the
Development of Field Programmable Analog Arrays for Space Applications," IEEE
[69] A. Stoica, D. Keymeulen, R. Zebulum, S. Katkoori, P. Fernando, H. Sankaran, M. Mojarradi, and T. Daud, “Self-Reconfigurable Analog Array Integrated Circuit
Architecture for Space Applications,” NASA/ESA Conference on Adaptive Hardware and
Systems, June 22-25 2008.
[70] A. Thompson, “Exploring beyond the scope of human design: Automatic generation of
FPGA configurations through artificial evolution,” 8th Annual Advanced PLD and FPGA conference, 1998.
[71] L. Sekanina and S. Friedl, “On routine implementation of virtual evolvable devices using
COMBO6,” Proceedings of the 2004 NASA/DoD conference on Evolvable Hardware, pp.
63-70, 2004.
[72] D. Laketic and P. C. Haddow, “Extreme Temperature Electronics – from Materials to
Bio-inspired Adaptation,” Proceedings of the second NASA/ESA conference on Adaptive
Hardware and Systems, 2007.
[73] K. Mizuno, N. Ohta, F. Kitagawa, and H. Nagase, “Analog CMOS IC for high-
temperature operation with leakage current compensation,” 4th International High Temperature Electronics Conference, June 1998.
[74] S. Terry, B. Blalock, J. Jackson, S. Chen, C. Durisety, M. Mojarradi, and E. Kolawa, “Development of robust analog and mixed-signal electronics for extreme environment
electronics,” Proceedings of IEEE Aerospace Conference, March 2004.
[75] F. Shoucair, “Design considerations in high temperature analog CMOS ICs,” in IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol: CHMT-9, no.3, pp. 242-251, 1986.
[76] J. Haslett, F. Trofimenkoff, I.Finvers, F.Sabouri, and R.Smallwood, “High Temperature
Electronics using Silicon Technology,” in Proceedings of IEEE International Solid State
Circuits Conference, February 1996.
[77] A. Stoica, “Toward evolvable hardware chips: experiments with a programmable
transistor array,” Proceedings of the 7th International conference on Micro-electronics for Neural, Fuzzy, and Bio-inspired systems, pp. 156-162, 1999.
[78] A. Stoica, R. Zebulum, D. Keymeulen, R. Tawel, T. Daud, and A. Thakoor,
“Reconfigurable VLSI Architectures for Evolvable Hardware: From experimental FPTAs
to Evolution-oriented chips,” IEEE Transactions on VLSI systems, vol: 9(1), pp. 227-232,
February 2001.
[79] A. Stoica, D. Keymeulen, and R. Zebulum, “Evolvable Hardware Solutions for Extreme
Temperature Electronics,” pp. 93-97, 2001.
[80] R. S. Zebulum, D. Keymeulen, J. Neff, R. Rajeshuni, T. Daud, and A. Stoica, “Extreme
Temperature Electronics using a Reconfigurable Analog Array,” 2006.
131
[82] A. Stoica, R. S. Zebulum, D. Keymeulen, R. Ramesham, J. Neff, and S. Katkoori, “Temperature-Adaptive Circuits on Reconfigurable Analog Arrays”, First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), pp. 28-31, 15-18 June 2006. [83] P. Fernando, H. Sankaran, S. Katkoori, D. Keymeulen, A. Stoica, R. Zebulum, and R.
Rajeshuni, “A customizable FPGA IP core implementation of a general purpose Genetic
Algorithm engine,” Proceedings of IEEE International Symposium on Parallel and
ABOUT THE AUTHOR
Pradeep Ruben Fernando received a Bachelor of Engineering Degree in Computer Science and Engineering from the University of Madras in 2002 and a Master of Science Degree in
Computer Engineering from the University of South Florida in 2006. He was admitted into the Ph.D. program at the University of South Florida in the summer of 2005. While in the Ph.D. program, Pradeep has co-authored several technical publications and presented papers at technical conferences.