LAC—Legacy Access Control Register

This 8-bit register controls steering of MDA cycles and a fixed DRAM hole from 15–

16

MB.

There can only be at most one MDA device in the system.

B/D/F/Type: 0/0/0/PCI

Address Offset: 87h

Reset Value: 00h

Access: RW

Size: 8 bits

BIOS Optimal Default 0h

Bit Access Reset _Value RST/_PWR Description

7 RW 0b Uncore

Hole Enable (HEN)

This field enables a memory hole in DRAM space. The DRAM that lies "behind" this space is not remapped.

0 = No memory hole.

1 = Memory hole from 15 MB to 16 MB. This bit is Intel TXT lockable.

6:4 RO 0h Reserved (RSVD)

3 RW 0b Uncore

PEG60 MDA Present (MDAP60)

This bit works with the VGA Enable bits in the BCTRL register of Device 6 Function 0 to control the routing of processor initiated transactions targeting MDA compatible I/O and memory address ranges. This bit should not be set if Device 6 VGA Enable bit is not set.

If Device 6 Function 0 VGA enable bit is not set, then accesses to I/O address range x3BCh-x3BFh remain on the backbone. If the VGA enable bit is set and MDA is not present, then accesses to I/O address range x3BCh-x3BFh are forwarded to PCI Express* through Device 6 Function 0 if the address is within the corresponding IOBASE and IOLIMIT, otherwise they remain on the backbone.

MDA resources are defined as the following: Memory: 0B0000h–0B7FFFh

I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh,

(including ISA address aliases, A[15:10] are not used in decode)

Any I/O reference that includes the I/O locations listed above, or their aliases, will remain on the backbone even if the reference also includes I/O locations not listed above.

The following table shows the behavior for all combinations of MDA and VGA:

VGAEN MDAP Description

0 0 All References to MDA and VGA space are not claimed by Device 6 Function 0.

0 1 Illegal combination

1 0 All VGA and MDA references are routed to PCI Express Graphics Attach Device 6 function 0.

1 1 All VGA references are routed to PCI Express Graphics Attach Device 6 Function 0. MDA references are not claimed by Device 6 Function 0.

VGA and MDA memory cycles can only be routed across PEG60 when MAE (PCICMD60[1]) is set. VGA and MDA I/O cycles can only be routed across PEG60 if IOAE (PCICMD60[0]) is set.

2 RW 0b Uncore

PEG12 MDA Present (MDAP12)

This bit works with the VGA Enable bits in the BCTRL register of Device 1 Function 2 to control the routing of processor initiated transactions targeting MDA compatible I/O and memory address ranges. This bit should not be set if Device 1 Function 2 VGA Enable bit is not set.

If Device 1 Function 2 VGA enable bit is not set, then accesses to I/O address range x3BCh-x3BFh remain on the backbone. If the VGA enable bit is set and MDA is not present, then accesses to I/O address range x3BCh–x3BFh are forwarded to PCI Express through Device 1 Function 2 if the address is within the corresponding IOBASE and IOLIMIT, otherwise they remain on the backbone.

MDA resources are defined as the following: Memory: 0B0000h–0B7FFFh

I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh, (including ISA address aliases, A[15:10] are not used in decode)

Any I/O reference that includes the I/O locations listed above, or their aliases, will remain on the backbone even if the reference also includes I/O locations not listed above.

The following table shows the behavior for all combinations of MDA and VGA:

VGAEN MDAP Description

0 0 All References to MDA and VGA space are not claimed by Device 1 Function 2. 0 1 Illegal combination

1 0 All VGA and MDA references are routed to PCI Express Graphics Attach Device 1 Function 2.

1 1 All VGA references are routed to PCI Express Graphics Attach Device 1 Function 2. MDA references are not claimed by Device 1 Function 2.

VGA and MDA memory cycles can only be routed across PEG12 when MAE (PCICMD12[1]) is set. VGA and MDA I/O cycles can only be routed across PEG12 if IOAE (PCICMD12[0]) is set.

B/D/F/Type: 0/0/0/PCI

Address Offset: 87h

Reset Value: 00h

Access: RW

Size: 8 bits

BIOS Optimal Default 0h

1 RW 0b Uncore

PEG11 MDA Present (MDAP11)

This bit works with the VGA Enable bits in the BCTRL register of Device 1 Function 1 to control the routing of processor initiated transactions targeting MDA compatible I/O and memory address ranges. This bit should not be set if Device 1 Function 1 VGA Enable bit is not set.

If Device 1 Function 1 VGA enable bit is not set, then accesses to I/O address range x3BCh-x3BFh remain on the backbone. If the VGA enable bit is set and MDA is not present, then accesses to I/O address range x3BCh-x3BFh are forwarded to PCI Express* through Device 1 Function 1 if the address is within the corresponding IOBASE and IOLIMIT, otherwise they remain on the backbone.

MDA resources are defined as the following: Memory: 0B0000h–0B7FFFh

I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh,

(including ISA address aliases, A[15:10] are not used in decode)

Any I/O reference that includes the I/O locations listed above, or their aliases, will remain on the backbone even if the reference also includes I/O locations not listed above.

The following table shows the behavior for all combinations of MDA and VGA:

VGAEN MDAP Description

0 0 All References to MDA and VGA space are not claimed by Device 1 Function 1. 0 1 Illegal combination

1 0 All VGA and MDA references are routed to PCI Express Graphics Attach Device 1 Function 1.

1 1 All VGA references are routed to PCI Express Graphics Attach Device 1 Function 1. MDA references are not claimed by Device 1 Function 1.

VGA and MDA memory cycles can only be routed across PEG11 when MAE (PCICMD11[1]) is set. VGA and MDA I/O cycles can only be routed across PEG11 if IOAE (PCICMD11[0]) is set.

B/D/F/Type: 0/0/0/PCI

Address Offset: 87h

Reset Value: 00h

Access: RW

Size: 8 bits

BIOS Optimal Default 0h

0 RW 0b Uncore

PEG10 MDA Present (MDAP10)

This bit works with the VGA Enable bits in the BCTRL register of Device 1 Function 0 to control the routing of processor initiated transactions targeting MDA compatible I/O and memory address ranges. This bit should not be set if Device 1 Function 0 VGA Enable bit is not set.

If Device 1 Function 0 VGA enable bit is not set, then accesses to I/O address range x3BCh–x3BFh remain on the backbone. If the VGA enable bit is set and MDA is not present, then accesses to I/O address range x3BCh–x3BFh are forwarded to PCI Express through Device 1 Function 0 if the address is within the corresponding IOBASE and IOLIMIT, otherwise they remain on the backbone.

MDA resources are defined as the following: Memory: 0B0000h–0B7FFFh

I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh, (including ISA address aliases, A[15:10] are not used in decode)

Any I/O reference that includes the I/O locations listed above, or their aliases, will remain on the backbone even if the reference also includes I/O locations not listed above.

The following table shows the behavior for all combinations of MDA and VGA:

VGAEN MDAP Description

0 0 All References to MDA and VGA space are not claimed by Device 1 Function 0. 0 1 Illegal combination

1 0 All VGA and MDA references are routed to PCI Express Graphics Attach Device 1 Function 0.

1 1 All VGA references are routed to PCI Express Graphics Attach Device 1 Function 0. MDA references are not claimed by Device 1 Function 0.

VGA and MDA memory cycles can only be routed across PEG10 when MAE (PCICMD10[1]) is set. VGA and MDA I/O cycles can only be routed across PEG10 if IOAE (PCICMD10[0]) is set.

B/D/F/Type: 0/0/0/PCI

Address Offset: 87h

Reset Value: 00h

Access: RW

Size: 8 bits

BIOS Optimal Default 0h

2.5.29

REMAPBASE—Remap Base Address Register