Low thermal budget technique

P-type MOS capacitors with heavily doped n-type substrate were fabricated on 3.84° off-axis (0001) Si face, n+ (sub)/p+ (1017 cm-3, 5 µm)/p- (6.7 × 1015 cm-3, 1 µm) epitaxial 4H-SiC (0001) wafers supplied by Cree. Firstly, the samples were cleaned with Piranha solution followed by the standard Radio Company of America (RCA) cleaning procedure. The cleaning process details are described in section 3.5.1. Photoresist depositions for the photolithography processes were carried out in an EMS 6000 photo resist spinner, using AZ 5214E photoresist at a spin velocity of 4000 rpm for 40 s, resulting in a photoresist thickness of 1.3 µm. Then, the photoresist was patterned using a Karl Suss MJB-3 Aligner and the designated mask, and this step was performed in every lithography step. The fabrication steps for p-type MOS capacitors were carried out as follow:

 Definition of the mesa structure: Mesa structures were created for every device for electrical isolation. A Mesa Mask (Table 4.1-1) was used to pattern the photoresist before 7 nm of Titanium (Ti) as the adhesion layer and 120 nm of Nickel (Ni) were deposited using BOC-Edwards auto e-beam evaporators as the etching mask. The metal was lifted-off using N-Methyl-2-pyrrolidone (NMP) for 3 min in ultrasonic bath following by Isopropanol (IPA) cleaning. Next, the samples were etched using the Plasma Therm 790 Reactive Ion Etching (RIE) process. This process was performed for 80 min in order to completely etch to a 5 µm depth. The remaining metal was then removed by dipping in Aluminium (Al) etchant for 30 min in the ultrasonic bath followed by 2 min of a buffered oxide etch (BOE) dip.

 P- _{epi-layer etching: The PPLUS Mask (Table 4.1-2) was patterned on the photoresist}

and similar processes as above were repeated with a metal deposition of 7 nm Ti and 50 nm Ni as a mask for a 1 µm 4H-SiC etch. This etching process was performed to open a contact on the doped p+ epilayer (NA= 1 × 1017 cm-3). Then the metal removal

process using Al etchant and BOE was undertaken. After this stage, the following steps vary depending on the type of oxide to be grown.

In the typical thermal oxidation technique for MOS fabrication, the contact formation with metal deposition and metal annealing were performed after oxide growth as the last step. In such case, the oxide may be exposed to a high temperature during the metal annealing process. This will produce an additional SiO2 layer and

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Unlike the standard thermal oxidation technique, the thermal budget technique requires modifications in order to protect the 4H-SiC surface from exposure to higher temperatures. Figure 4.1 illustrates the modification of the process in order to achieve a low thermal budget gate oxide.

 Metal contact formation: Next, after the etching process, samples were patterned by using the Metal 1 Mask (Table 4.1-3). Then, a stack of metal consisting of 5 nm Ti / 45 nm Al / 15 nm Ti / 45 nm Al / 10 nm Ti was evaporated by e-beam to form metal- semiconductor contacts. After the lift-off process, post metallisation annealing (PMA) was performed at 1000 °C for 3 min in a high vacuum chamber using Jet First 200 Rapid Thermal Processing (RTP). A chamber pressure of 7 × 10-4 mbar was recorded during this annealing. This step is necessary in order to produce stable ohmic contact behaviour [115]. Then, a 100 nm Si3N4 layer was deposited at 220 °C using Plasma

Enhanced Chemical Vapour Deposition (PECVD). This layer is used to protect the metal contact during the subsequent oxidation process and also to create an additional isolation layer between the oxide gate and metal contact [116].

 Gate oxide formation: Then samples were patterned using a Dielectric Mask (Table 4.1-4) before the Si3N4 layer was etched over the gate area using BOE for 1 min, where

photoresist was used as a mask for this etching. After the etching and the removal of the photoresist, the samples were oxidised using RTP at several low temperatures for a short duration. The thicknesses of these SiO2 layers were determined by Angle

Resolved X-Ray Photoelectron Spectroscopy (ARXPS) compared to control samples oxidised alongside. Then the gate insulator stack was completed with the deposition of 40 nm of aluminium oxide (Al2O3) by Atomic Layer Deposition (ALD) immediately

after oxidation. Adduct-grade trimethylaluminium (TMA) and H2O were used as

precursors and were transported to the reaction chamber in vapour draw with a nitrogen (N2) carrier gas. Deposition was performed at 200 °C at a chamber pressure of

600mTorr with pulse/purge lengths of 0.1/4 s for TMA and 0.1/6 s for H2O

respectively.

 Gate electrode formation: Next, the samples were patterned with the Metal 2 Mask (Table 4.1-5) before gate contact was formed by the deposition of 150 nm Al. The devices were completed with a contact opening in the Si3N4 layer with RIE using

photoresist as a mask as depicted in Figure 4.2. Figure 4.3 shows a microscopic image of the fabricated p-type MOS capacitors using the low thermal budget technique.

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Table 4.1: Fabrication steps with mask configuration of low thermal budget MOS capacitor

Cross Sectional View Mask Set

1) Mesa structure

Mesa Mask

2) PPLUS etch

PPLUS Mask

3) Metal contact deposition and

annealing _{Metal 1 Mask}

4) Oxidation and Al2O3 deposition

Dielectric Mask

Gate contact metallisation

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Figure 4.1: MOS fabrication process with a) low thermal budget technique and b) standard thermal oxidation technique

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Figure 4.3: Microscopic image of fabricated p-type MOS capacitors using low thermal budget technique

4.2.2 1150 °C oxidation technique

For the control MOS capacitor, a surface preparation process was performed before the gate oxide growth to fully treat the surface. The sacrificial oxide was oxidised at 1150 °C for 60 min in dry O2 ambient in the furnace. Then, this oxide layer was removed by wet etching using BOE

for 30 s to produce the renewed 4H-SiC surface. Then, the critical step to produce gate oxide followed. The samples were oxidised at 1150 °C for 180 min in an O2 flow rate of 150 sccm in

the furnace, resulting in a SiO2 layer of 28 nm thick. This gate oxide was then covered by

photoresist, allowing the metallisation of the back contacts. To form metal back contacts, a similar stack of metal consisting of Al and Ti was evaporated using the e-beam evaporator, followed by PMA using RTP at 1000 °C for 3 min. Finally, the devices were completed with the deposition of 100 nm Al to form the gate contacts.