Management of Concurrent Multiplication Units

The management of the multiplication tasks is handled by the micro-machine and its virtualization schemes by distributing multiplication tasks to one of the multiple hardware multiplier units in the architecture. Due to the hierarchical architecture of the different arithmetic layers the coprocessor is highly modu- larized and able to process the different ECC-arithmetic operations on various configurations of basic finite field processing units. The flexibility of the micro- machine and virtualization unit is of high priority, so that for each point-doubling or point addition-operation a different data path configuration can be executed during the execution of the same superior scalar multiplication of the basis point.

Due to the virtualization scheme on the data path, the demultiplexing bus ar- chitecture and the shared BRAM data storage, the micro-machine in conjunction with the virtualizing schemes can configure the data path efficiently. For partially reconfiguring one of the hardware multiplier units the management unit has to distribute its workload on the remaining two multipliers. The VLIW instruction set allows the micro-machine and the virtualization unit to remap assigned mul- tiplication tasks to another hardware unit. Thus the concept of dynamic binding in this architecture is similarly solved as in the application example of the AES. Also in this case the virtualization concept is the interface between the software part of the architecture and the hardware segment. The software controls the data flow by reconfiguring the data path structure of the ECC-coprocessor by the VLIW.

6.2.2.1 Virtualization Scheme

The central element of the virtualization scheme for the ECC Mutate is the VLIW instruction set. Table 6.2 depicts the architecture of the instruction set of the ECC-coprocessor. An opcode sequence in order to trigger one operation on the data path may have up to three different, sequential instruction types. These instruction types have a fixed bit length of 32 bits, but the information a bit position is containing changes based on the interpretation of the instruction type, cf. Tab. 6.2. The three instruction types can only appear in a strict sequence with special conditions of the previous instruction type. Therefore, the instruction types do not need a header for identification purposes.

The instruction Type 1 is first sent to set up the initialization phase of an executing operation. This instruction type contains the needed information to configure the GF(p)-Alu component, cf. Fig. 6.4 and Tab. 6.2. In this phase the multiplexers in the GF(p)-ALU as well as on the data memory are configured. The third least significant bit, bit 2, is an indication wether the second instruction type is following or maybe the third instruction type is the successor of the current instruction Type 1.

In case a memory access is indicated by the field MA the successor opcode is interpreted as an instruction Type 2 and sets the corresponding access infor- mation to the data memory. If a constant value access is indicated by the value "00" in the field AI or the field BI the last opcode command of the initialization phase is interpreted as instruction Type 3. After the initialization phase with one, two, or three opcode instructions the data transfer is started and the data is processed on the data path.

The internal virtualization scheme of the ECC-coprocessor differs from its implementation for the previous application on a symmetrical block cipher. The virtualization layer of the AES Mutate consists of micro-programs selected by

6.2. Realization of the Mutating Data Path 127

Table 6.2: VLIW structure of the ECC-coprocessor

Instruction Type 1

Bit 31:30 29:28 27:25 24:22 21:16 15:11 10:5 4:3 2 1 0

Function AI BI RES1 RES2 loadA loadB outRES AS MA RT ST

Instruction Type 2

Bit 31:30 29:20 19 18 17:16 15:6 5 4 3:0

Function DIA ADDRA ENA WEA DIB ADDRB ENB WEB not used

Instruction Type 3

Bit 31:28 27:24 23:0

Function DIROPA DIROPB not used

Function Description

AI /BI Selects the input of port A/B of the GF(p)-ALU.

RES1/RES2 Selects the output of a finite field arithmetic unit (FFAU) and provides it to the output 1/2 of the GF(p)-ALU.

loadA/LoadB Identifies the FFAU, if the current value on the internal busses are valid to process.

outRES Informs the corresponding FFAU that the result is requested from the data transfer.

AS Configures the corresponding subtractor-adder-unit to perform a subtraction or an addition.

MA Request a memory access.

RT Last command of the micro-program.

ST Start signal for the FFAU, which was provided with new data. DIA/DIB Sets up the multiplexer at the data memory inputs.

ADDRA/ADDRB Memory address of where to store in or to read from the data memory.

ENA/ENB Enables the memory port A/B for data transfer.

WEA/WEB Indicates if data is stored to the enabled port or data is read from the enabled port.

DIROPA/DIROPB Addresses the constant value in the pre-calculated curve and algorithm specific constants.

a random number and a scrambling unit manipulating the incoming opcode se- quences from the micro-programs. The virtualization layer of the ECC Mutate coprocessor only consist of a bigger set of micro-programs conducting the ECC-

Table 6.3: Supported point representations of the ECC Mutate coprocessor Projective representation Point representation

Affine _P(x,y)

Standart projective without y _{P(X/Z,-,Z) with Z 6=0} Standart projective with y _{P(X/Z,Y/Z,Z) with Z 6=0} Jacobian with y _P(X/Z2_,Y/Z3_{,Z) with Z 6=0}

Jacobian Chudnovsky with y P(X/Z2_,Y/Z3_,Z,Z2_,Z3_{) with Z 6=0}

arithmetic operations with a different set of hardware resources in various inter- mediate representations. For each utilization number of multipliers and possible value representations a micro-program is stored inside the BRAM.