An electrical test is the process of testing each contact on a component to ensure it matches the component electrical properties such as the functionality of the device. It can detect defects caused by Electrostatic Discharge (ESD) damage, internal physical damage caused by heat damage, and electrical overstress. For this AES chip, an unpowered electrical test was completed by switching off the component, without adding any stimulus to the electrical component. When the result is satisfactory, the functional test will be set up.
The physical testing of the fabricated chip was performed to verify the functionality of the AES crypto-processor chip, and make sure the results were identical to the simulation results in term of functionality. Power analysis and propagation delay were not performed to the fabricated chip because it required additional hardware with advanced equipment which is not available in the university. The functional verification results during power-on are presented. The additional circuitry and testing system are interfacing with the AES chip in order to perform a test. After a connection is
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established, the values are updated every second. The test circuit setup used for field testing is shown in the figure below (Figure 7.11). Functional verification is performed with 8-bit input of the data block and initial cipher key to produce 8-bit output of data. The same set of test vectors from NIST as the section 7.4.1 were used to verify the encryption and decryption process.
The operation of this chip is controlled by four logic-level inputs; clock, reset, enable and enc_dec. The encryption and decryption process depends upon the signal enc_dec, when enc is selected, it signals the datapath that the encryption needs to be performed; when dec is selected, the decryption will be performed. Signal reset is a global signal used to reset the chip. En signal is an enable signal that enables the operation of the chip when it is selected. The chip was also tested for verification 8-bit output of sub- block MixColumn and key round from the Key Scheduling unit.
Figure 7.10 ML505 FPGA board for test vectors generator
A testing circuit has been developed by interfacing the AES chip to the Field Programmable Gate Array (FPGA). Figure 7.10 shows the ML505 evaluation board that has been used in the testing. The actual test results obtained with test vectors generated and output displayed using the ML505 Xilinx FPGA Development board using the verification methodologies is described as follows:
XGI Expansion Interface Power on switch GPIO DIP switch Virtex-5 XC5VLX50T FPGA
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a. The FPGA Test System was developed and implemented using a FPGA ML505 board that consists of a Test Pattern Generator and Output Buffer Comparator. The Test Pattern Generator is used to generate a selected 20 set of test vectors from FIPS 197 for data block and key initial described in VHDL programming and carried out using Xilinx software ISE 9.1. This test vector was used to debug and verify the AES chip by interfacing the chip with the FPGA board. An Output Buffer Comparator was used to display the results generated from an AES chip in the PC, using ChipScope software and compare the results with the reference output. If the results are not the same, it displays ‘1’ at the comparative output.
b. A control input bit stream, including a set of test vectors, clock signal 100MHz and reset signal from FPGA board are interfaced to the AES chip by an XGI Expansion Interface, to provide the input for the AES chip. The hardware testing setup is illustrated in Figure 7.11. Data inputs are sent from the FPGA board to the chip to process the encryption or decryption algorithm. Enc_dec and enable signals are connected directly from external switches to the AES chip. The AES chip then transmits the data results to the FPGA board to display the output on the computer.
135 Text_gen. vhd AES Chip DUT Key_gen. vhd Cipher_gen. vhd Comparator. vhd
FPGA Test System
Test Pattern Generator
Buffer Comparator ChipScope software Input clk rstn Clk_out Rstn_out Data_in Key_in Cipher_in Data_out MixColumn_out Keyround_out Output_comparator 4 8 8 8 8 8 8 8 8 8 8 en Enc_dec
Figure 7.11 Hardware connection setup for AES testing
c. A printed circuit board for the AES chip is made and connected together to the FPGA board. As the output voltage from FPGA is 3.3V, and the AES chip only operates at in 0.8V, FPGA voltage output is translated to 0.8V using a 4-bit dual supply translating transceiver, 74AVC4T245. It is also used to translate from 0.8V to 3.3V to display the AES output in FPGA. AES output is connected back to FPGA logic test system to display signals during measurement and compare with expected output using Xilinx ChipScope software.
d. The functional test included the following steps: i) Test input signal of Reset and Enable
a. Reset the chip, this clears the registers and counters that affect the output of the system.
b. Disable the chip: causes no operation of the system.
ii) Test Counter Mod 10 in the system to produce the output of the counter, (q3, q2,
q1, q0) and Sel_data requiring 100MHz clock; set the enable and reset=0.
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a. Set the enable, reset=0 and set the Enc_Dec =1 for encryption
b. Give 100 MHz clock and a sequence 8-bit data in 16 cycles clock for Data_in and Key_in. The sequence is repeated for 20 sets of test vectors for the encryption and decryption process in the AES system.
e. Logic analyzer Textronix TLA5202 will also used to display the clock, the inputs and outputs of the AES chip from the FPGA to get the different view of the AES output. The oscilloscope is used for power measurement of the AES chip voltage.
(a) (b)
(c)
Figure 7.12 Circuit testing for AES (a) PCB with the test socket for AES and 4-bit dual supply translating transceiver, (b) Logic analyzer to display the output, and (c) Circuit
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