Like every other subsystem in the 86 0 0 , the F Box is control led by m icrocode . Microcode offers a structured yet tl cxiblc and economic way of i mplementing the control fu nctions . For complex instructions-such as polynom ial eval uati ons- m icrocode is esse ntial for sequencing through the various steps . Even for the basic operations like add and mu ltiply, m icrocode is helpfu l in dealing with u n usual condit ions . The achievement of a compact hardware design depended on the use of hardware units like adders and shifters for m u l tiple pu rposes, and m i crocode prov ides s u ffi c i e n t c o n t r o l to ach ieve that des ign. Moreover, microcode con trol al lowed us the tl exibil ity to implement fa u l t detection and fa ult isolation procedures so that manufacturing and fie ld service cou ld effect repairs using m i crocoded d i agnostic programs.
We had to make several design restrictions in order to cycle the control store du ring each F Box cycle. For example, each mod u le needed its own m icrosequencer and control store. And e x c e p t for i n i t i a l d i s pa t c h i n g , t h e two microcodes run independently.
Digital Technictll journal No. I August I 'J8'i
We latched the m icroword i nternals to the MCAs that used them in order to save propaga tion t i me and to e l i m i nate the need for addi tional MSI components. The m icronelds were highly encoded due to the l i mited nu mber of MCA pins ava i lable. That high l eve l of encoding allowed us to make the whole control store rel atively narrow-4 8 bits for the adder module and 4 0 bits for the m u l t i p lier modu l e . That makes it easier for the F Box to access the con trol store dur i ng each cycle. I nside the gate array, the F Box can decode the m icrocode i nto a large nu mber of control functions , some of which are appli cable over several cycles. The control signals are pipel ined along with the data and the F Box gradual l y decodes those sig nals at each stage (see Figure 8 ) . The resu l ts of these data operations are someti mes fed back into later decode stages. This m icrocode style was needed , in particular, to accommodate the pipe l i ned structure of the datapath , where sev era l operations take place s i m u l taneously.
The result of those design restrictions was a scheme i n which the m i crocontrol bits foUow the data for several cyc l e s , b e i ng fu rther decoded at each stage . For the majority of cases, the m icrocode is l ittle more than a decodi ng of the opcode, allowing the hardware to do a l ign ments, add i tions, normal izations, and rou nd ings. The m icrosequencer takes over only if the i nstruction does not fit the standard path and creates the needed resul t by using the avai lable hardware functions.
Funct1on
Data
Microcode
We had to define the operations at each cycle early in t he design stage in order to get this t ight fit between the m icrocode and the hard ware . That was possible due to the relatively sma l l nu mber of operations i nvolved in floating point processing.
The short cycle time of the F Box compl icates the control of m icrocoded branching. Each con trol store location contains a NEXT ADDRESS field. To change control tlow, the m icrocode se lects up to three branch conditions at a t i m e . The OR o f these condi tions a n d t h e low three address bits select the next m icroword to be execu ted. The selectors are contro lled by a branch enable (BEN) fie l d i n the m icroword . The BEN fie ld of a m icroinstruction does not affect the next m icro-PC but does affect the one fol lowing i t . (This is ca lled "de layed branch ing. " ) The delayed-branching algorithm com p l i c a t e s t h e m i c r o p r o g ra m m i n g , s i n c e b r a n c h e s - i n - progress a lways h a v e t o b e accoun ted for. Figure 9 shows t h e d iffe rent i n p u t s a n d h ow t h e y a ffe c t t h e n e x t m icroaddress.
The microsequencer contains no sta l l signals. I nstead , the m icrocode branches on conditions that w i l l force it to change flow. Aga i n , that m icrocode d e s i gn s i m p l i fies the hardware design, s i nce stall conditions can be encoded i nto normal control signals.
The I Box sends the opcode of the i nstruction to the mu l t i p l ier modu l e . There the opcode is used to address the d ispatch RAl\1 conta i n i ng
FunCtiOn
Latch
Latch Latch
Figu re 8 Microcode Co ntrol in the F Box
Digital Tech11ical journal 5 1
The F Box. Floating Point in the VA X 8600 .�:ystem
New Instruction Fork
E Box Trap
Jump Call/Return Address Parity Error Address D1agnostic Address Next M1cro-PC Micro-PC Control Store (51 2 Bits x 48 Bits)
Branch Enable (BEN)
M1croword
Fig ure lJ The F Box Microsequencer
the start ing microcode address for the instruc tion. The same starting address is used for both m icrosequencers. The dispatch RAM also con tains format bits that are used to control certain hardware operat ions . An instru ction register decode ( I RD) signal from the E 13ox triggers the start of a new instruction . A " flush" signal from the ( 13ox is used to reset the microse quencer in case of a change in the instruction stream , nor mally due to a branch or an exception . Without this signa l , due to the pipe li ning of i nstruc tions, the F 13ox might have started on a floating point instruction fo llowing the branch. Such an act ion w o u l d have p u t the F Box o u t of sequence with the I Box and E Box.
The E Box has the abil ity to trap the F Box to various m icrocode rou tines. That abil ity is use ful when the program wants to use the F Box to execute s u b ro u t i n e fu nct io ns i n c o m p l e x instructions, or when t h e program wants to write customer-origi nated m i crocode in the E Box .