A.1 ARM Cortex-M0
The information in this section gives an overview of the ARM Cortex-M0 microprocessor used in Chapters3,4 and 5 of this thesis. The information presented in this section is gathered from the ARM Cortex-M0 Generic User Guide available from ARM [160] and The Definitive Guide to the ARM Cortex-M0 by Joseph Yiu [167].
The ARM Cortex-M0 was chosen as a test case because of its relevance to low perfor-mance energy constrained applications. The ARM Cortex-M0 is, at time of writing, the smallest microprocessor available from ARM with a reported 12,000 logic gates in its minimum configuration. A simplified block diagram of the Cortex-M0 processor is shown in Fig. A.1. The processor is made up of a number of essential units and op-tional units. The first opop-tional unit is the Wake-up Interrupt Controller (WIC) which enables support for a power management unit. Using this optional unit the processor can be powered down while there is nothing to be executed and the WIC can monitor incoming interrupts. If an interrupt is detected the WIC can interface with a power management unit to enable the processor for execution. The optional debug hardware provides access to the system’s bus. It contains functional blocks to handle breakpoints and watchpoints in developer code so that when a debug event occurs, the processor can be put in a halted state while the state of the processor is examined. Throughout this thesis the debug hardware has been omitted from the processor to reduce area and power. The Nested Vector Interrupt Controller (NVIC), Processor Core and Bus Ma-trix make up the essential blocks within the processor. The NVIC can be configured to have up to 32-bit interrupt request signals in addition to a single nonmaskable interrupt (NMI). The purpose of the NVIC is to judge the priority of incoming interrupts so that it can automatically handle the execution of nested interrupts. When an interrupt is requested the NVIC interfaces with the processor so that it can call and execute the cor-rect interrupt service routine. The purpose of the NMI is an interrupt for high priority
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Cortex-M0 Components
Figure A.1: Block diagram of the Cortex-M0 processor
tasks that may, for example, be safety critical and cannot be disabled unlike the other interrupts in the processor. When the NMI is requested, it has the highest priority out of all interrupts and guarantees the interrupt service routine will be executed for the requested interrupt.
The processor core in Fig. A.1 makes up the bulk of the processor and contains the register banks, the ALU, datapath and control logic. The register bank is made up of 12 general purpose registers, a stack pointer register used for the address to the stack, a link register used for storing the return address of a subroutine and the program counter which stores the address of the current instruction being executed. In addition to the main register bank there are three main special registers: program status register which contains information about the program execution and ALU flags, the Primask register which is used for blocking all of the interrupts except the NMI in the NVIC and finally the Control register which is used for control flow. The ALU is made up of an addition and logical unit, a multiplier, and a shift and permute unit as was shown in Chapter 3, Fig. 3.15. Depending on the application requirements, the multiplier in the Cortex-M0 can be configured to be a large, fast single cycle multiplier for higher performance systems, or a small 32 cycle multiplier for low performance systems.
The entire system uses a von Neumann architecture with a single unified 32-bit wide data and instruction bus. The bus used by the Cortex-M0 is the Advanced Microcontroller Bus Architecture (AMBA) AHB-Lite specification developed by ARM. The micropro-cessor is based on the ARMv6-MTM architecture and is based on the classic load-store architecture with a 3 stage pipeline consisting of instruction fetch, instruction decode and instruction execute. The processor supports most of the Thumb-2 instruction set in-troduced in 2003. The Thumb-2 instruction set is a combination of the original Thumb instruction set consisting of only 16-bit instructions with an addition of a number of 32-bit Thumb instructions. The purpose of this was to enable the Thumb instruction set to be capable of all the instructions that could previously only be carried out by the
ARM instruction set. The result of this is a smaller code footprint, thanks to the 16-bit instructions, but approximately the same level of performance as when using the ARM instruction set. In the ARM Cortex-M0, the entirety of the 16-bit Thumb instruction set is supported but only a subset of the 32-bit Thumb instructions are supported. In total, 56 base instructions are available in the Cortex-M0: 50, 16-bit Thumb and 6, 32-bit Thumb instructions. Despite, the Cortex-M0’s small size and limited instruction set the capability of the processor makes it much more energy efficient than equivalent 8-bit and 16-bit processors. Throughput is reported to be 3x better than the popular Texas Instruments MSP430 and 2x better than the PIC24 and so for a given performance the Cortex-M0 could operate with much lower clock frequency and power compared to its 8-bit and 16-bit counterparts [167].