Miniaturization and Monolithic Integration of Optical Components (Nanophotonics)

Economically, photonic integrated circuits (PICs) are considered to be essential for driving down costs of optical subassemblies (see Section 12). Higher levels of monolithic integration allows greater on-chip functionality, higher reliability, potential for higher data rates, and most importantly, lower component and operating costs to the system providers. Monolithic integration of optical components on silicon, GaAs, and InP substrates is continuing to get more sophisticated. For an example of current technology, optical component count on fielded dense wavelength division multiplexing (DWDM) laser transmitter PICs is in the range of 50 to 100. It is predicted that future PICs would require integration of several hundred, if not thousands, of optical components. Integration on silicon is especially attractive because of the possibility of combining electrical and optical integrated circuit technologies (active and passive) on the same chip.

Recent work in Germany describes silicon-organic hybrid (SOH) devices fabricated on SOI substrates. The objective of this research is to exploit and combine the strong light confining characteristics of silicon optical waveguides with the highly non-linear optical properties of certain organic liquids to realize highly compact optical signal processing

components such as high speed Mach Zehnder (MZ) modulators and de-multiplexers for optical time domain multiplexed (OTDM) signals [7-1]. Examples include a 6 mm SOH device that demultiplexes a 120 Gbps data stream to 10 Gbps and an 80 µm long MZ modulator design capable of modulating at 100 Gbps rates with a drive voltage of only 1 V. The demultiplexer exploits the four-wave mixing (3^rd order intermodulation) phenomenon and the strong nonlinear

Another example of a complex (experimental) InP-based PIC is described in reference [7-2]. It is a packet forwarding chip (see diagram in Figure 7-1) that integrates a complete optical receiver incorporating two semiconductor optical pre-amplifiers (SOAs) with photodiode, and a transmitter incorporating a distributed Bragg reflector (DBR) laser followed by two electro-absorption modulators, a passive splitter and combiner and interconnecting ridge waveguides, all integrated on a 4.0 x 0.55 mm² die.

Figure 7-1:: Diagram of Field-Modulated Packet Forwarding Chip Depicting Wavelength Conversion and Label Writing Functions and Schematic of Fabricated Device Showing Integrated Components. Footprint Is

4.0 mm x 0.55 mm (From Ref. [7-2]). (40735)

Still another example of a miniature silicon-based photonic circuit is that of a non-blocking four-port bidirectional multi-wavelength message router [7-3]. The fabricated chip is approximately 0.3 mm on a side. A photomicrograph of the die is shown in Figure 7-2(a) and a color-coded example of its ability to route three different wavelengths (1538 nm, 1546 nm, and 1554 nm) incident on one port to the three other ports (or any other input/output port

combination) is shown in Figure 7-2(b). It employs eight micro-ring resonators which are essentially wavelength filters that are implemented on a CMOS-compatible silicon die. Each ring is a 20 μm-diameter silica optical waveguide with cross-sectional dimensions of 450 nm x 250 nm that incorporates a heater that tunes the filter (through the thermo-optic effect) by changing the temperature and hence the refractive index (RI) of the optical waveguide. Worst case insertion loss of the signal through the router is only1.3 dB.

Photomicrograph Color-Coded Routing Diagram North

South West

East

(a) (b)

Figure 7-2: A Non-Blocking Four-Port Bidirectional Multi-Wavelength Message Router a) Photomicrograph of Fabricated Device On A CMOS-Compatible Chip With Plan Dimensions 1/3 mm x 1/3mm and b) Color-Coded Routing Diagram Indicating Router In A Specific Configuration Routing Each Of Three Wavelengths

Incident On The North Port To One Of Three Output Ports (from Ref. [7-3]). (40794)

A futuristic optical transceiver concept for intra-board high speed chip-to-chip

communication such as might be used in a HPC system using CMOS-based photonic chips, is depicted in Figure 7-3 (taken from the slide presentation of reference [7-4]). The complete DWDM monolithic optical transceiver is fabricated on a CMOS chip incorporating an electro-optic (E-O) polymer electro-optical layer that contains the electro-optical circuit including silicon nitride waveguides, optical micro-ring resonator modulators and lateral metal-semiconductor-metal (MSM) germanium (Ge) photodetectors that are coupled to the SiN waveguides. A continuous wave (CW) multiple wavelength III-V laser array is off-chip and services all on-chip modulators.

The embedded micro-ring resonators are used for wavelength filtering and high-speed

wavelength-specific modulation of the light (using the E-O polymer to modulate the mode index of the SiN embedded optical waveguide). The CPU, memory, as well as the modulator drivers and amplifier electronics for the optical components are all contained in the CMOS chip directly below the optical layer.

Figure 7-3: Possible Structure for CMOS-Based Monolithic Transceivers Used for Chip-To-Chip Intra-Board Optical Communication As It Might Be Applied In A Futuristic HPC system. An Electro-Optic Polymer Layer Containing The Optical Circuit Is Applied Directly On Top Of The Silicon (From Ref. [7-4]).

(40795)

Finally, mention should be made of dense optical interconnects on-chip. Although there is some controversy among optical communication researchers whether intra-chip optical

communications makes sense even in the distant future, there is, nevertheless, on-going research in this field. Specifically, DARPA’s UNIC program seeks to explore the utility of CMOS-based intra-chip photonic interconnects for future high performance computing applications [7-5]. An argument made for the justification of this research is that the shear increase in computing power (because of continuing transistor advances) is outpacing the available bandwidth for processor-to-processor communications even at the chip level. A better balance of these two factors is needed, and on-chip optical interconnects is considered to be a potential way of achieving it. For this project, a dramatic miniaturization of optical components and power consumption of all active devices is key to the program. A power consumption target for an optical link of less than 0.01 pJ/bit has been espoused by the DARPA Program Manager.