Model of DC biasing circuitry components

Furthermore, in simulation, an accurate model to allocate the components of the DC biasing circuitry that will control the varactor diodes had to be designed. The slots original structure will be therefore slightly modified in order to fit the components the slots biasing circuity and varactor diodes.

After reviewing many options, the varactor Infineon BB833 was selected to be incorporated in the slots. This varactor diode offers a capacitance range from 0.5 pF to 10 pF when varying the input voltage from 30 V to 0 V respectively which is an appropriate range to explore. In order to control the input voltage in the varactors without being affected from external distortions from undesired RF signals a DC biasing network containing inductors acting as RF chokes has been implemented. Inductors allow only the DC pass and will block every other signal, including external high frequencies. Fixed capacitors used as DC blocks and of course the DC voltage source applied to the varactor diodes. This biasing network is shown in Fig. 29.

Fig. 29 Electronic diagram of DC biasing network to control varactor diodes.

This biasing network and its components will be allocated within each slot structure. A metallic pad was created to be the feeding point of the DC voltage that will control the varactors. This pad was separated by a gap of 2 mm in order to isolate it from the ground plane, acting as the connection node of the varactor diode which then will be connected to the ground plane and the DC block capacitors. Then in the opposite face of the board, near the feed lines, another pad will be allocated along with a metallic bias connecting it with the one in the ground plane. This second pad will be connected to the RF choke inductor and this last one to the DC voltage line. This distribution was carried out for each slot.

Fig. 30 (a) shows the ground plane view of this connection and Fig. 30 (b) the feed line view of the slot structure including the DC bias network components.

Fig. 30 Schematic allocation of components of DC biasing network.

In order to properly dimension the components of this network and place them on the board it was imperative to calculate the proper values for RF choke inductors and DC block capacitors including the packages dimensions. Referring to the reactance expressions, X is a magnitude that describes the opposition of capacitive and inductive loads face to electric current and depends on the frequency of the signal. Reactance is given by the expression 𝑋 = 𝑋_𝐿− 𝑋_𝑐 where XL is the inductive reactance and XC is the capacitive reactance given by 𝑋_𝐿 = 2𝜋𝑓𝐿 and 𝑋_𝐶 = 1

Based on the frequency ranges obtained in the original work one can consider the peak values for each band 1.12 GHz for band 1, 2.47 GHz for band 2 and 2.70 GHz for band 3 and in order to determine the values for L and C in the biasing network. In practice, when working in high frequencies one aims for high values of inductive reactance and low ones of capacitive reactance. After reviewing commercial values for inductors and capacitors in the market the selected values were for RF choke inductors L = 560 nH and DC block capacitors C = 380 pF and corroborated them using the reactance expressions as follows:

Xc values < 1 Ω:

Band 1 fmax value 1.12 GHz, C = 300 pF, 𝑋𝐶 = 1 2𝜋𝑓𝐶=

1

2𝜋(1.12 𝐺𝐻𝑧)(380 𝑝𝐹)= 0.473 Ω Band 2 fmax value 2.47 GHz, C = 300 pF, 𝑋_𝐶 = 1

2𝜋𝑓𝐶=

1

2𝜋(2.47 𝐺𝐻𝑧)(380 𝑝𝐹)= 0.214 Ω Band 3 fmax value 2.70 GHz, C = 300 pF, 𝑋_𝐶 =

1 2𝜋𝑓𝐶=

1

2𝜋(2.70 𝐺𝐻𝑧)(380 𝑝𝐹)= 0.196 Ω XL values > 1 KΩ:

Band 1 fmax value 1.12 GHz, L = 500 nH, 𝑋𝐿 = 2𝜋𝑓𝐿 = 2𝜋(1.12 𝐺𝐻𝑧)(560𝑛𝐻) = 3518.58 Ω Band 2 fmax value 2.47 GHz, L = 500 nH, 𝑋𝐿 = 2𝜋𝑓𝐿 = 2𝜋(2.47 𝐺𝐻𝑧)(560𝑛𝐻) = 7759.73 Ω Band 3 fmax value 2.70 GHz, L = 500 nH, 𝑋_𝐿 = 2𝜋𝑓𝐿 = 2𝜋(2.70 𝐺𝐻𝑧)(560𝑛𝐻) = 8482.30 Ω

As the calculations proved, the chosen values for L and C achieved low reactance values in the order of < 1 Ω for Xc and high reactance values in the order of > 1 KΩ for XL.

Once the value of components had been determined we allocated the space they would occupy in the board and distributed them by knowing their dimensions. Varactor diodes BB833 are available in package SOD-323 measuring 1.7 mm × 1.25 mm and two terminals of 0.8 mm × 0.6 mm covering a total are of 2.5 mm × 1.25 mm. DC block capacitors and RF choke inductors are both available in package 0603 measuring 1.6 mm × 0.8 mm. In order to fully assess the effects of the components in this biasing network the corresponding self-resonance frequency (SRF) must be considered as well. This SRF is the frequency associated to the internal and parasitic inductances and capacitance of their respective components. Every component can be considered as a LC equivalent circuit, the corresponding value for this is given by 𝑆𝑅𝐹 = 1

2𝜋√𝐿𝐶. Although the values for RF chokes and blocking capacitors has been superficially calculated without including the effect of SRFs for each component, an

appropriate assessment for this must be carried out in future work derived from this precedent. The footprint of these components was included in the CST models with their corresponding dimensions. Fig. 31 (a) shows the ground plane view and Fig. 31 (b) the dimensions of the gaps created in both faces and the DC voltage feeding lines for each slot structure. The biasing metallic element connects both pads, each pad has a perforation of 0.8 mm of diameter. The footprint of components was achieved as vacuum blocks with the dimensions of components were placed on the CST model.

The varactor diodes, DC block capacitors and RF choke inductors were modelled as RLC lumped elements with their respective properties and values. Internal inductance and resistance were replicated for the varactor diode after consulting the Infineon BB833 datasheet. While capacitors and inductors were just assigned their corresponding value.

Two methods to model the components were carried out as the CST software suite offers to create point to point and edge to edge lumped RLC elements. Firstly, the method of point to point lumped RLC components was assessed in the simulator. For this method only two points of the geometrical space are required, they are easy to create, faster to analyse but less accurate in terms of results as it provides a superficial estimation of the magnitude simulated from one point to other in the antenna geometry. Fig. 32 shows the allocation of the elements for both faces of the board.

On the other hand, the creation of edge to edge components required a physical model of the real components in the boards, for this purpose, the vacuum blocks created for the component’s footprint holding the real dimensions were used to develop the lumped elements. This method creates more precise lumped RLC elements that are more accurate. Fig. 33 shows the creation of edge to edge lumped elements.

Fig. 33 Modelling of edge to edge lumped components in simulator.

After many tests were carried out and as expected, the use of edge to edge lumped elements offers a more efficient and precise model of components, closer to the real-life components. In the simulated results in next section we will therefore discuss the results of the models holding edge to edge components. Finally, and as a summary, we will show the models for each prototype with their corresponding components and additional pads and lines in Fig. 34 (a) (b) and (c) for feed line views and (d), (e) and (f) for the ground plane views.