Modelling and implementation

Modelling and implementation of the various components and controllers are discussed in this section. All modelling was performed in DIgSILENT PowerFactory after testing of controllers’

functionalities in Matlab/Simulink. The implementation of CC and WPPC was performed in National Instruments’ LabView language on a real-time controller (PXI).

8.3.1 Overview

The overall, high-level block diagram of the model that was set up in PowerFactory is depicted in Figure 94. Standard static generator models are used to represent the WTG converters and are the interface between the controllers and the grid model. A VSC model is used to model the CGI, the control of which only clamps voltage and frequency to their reference value. For most of the tests performed here, a stiff voltage source would be sufficient to model the grid. However, one test

Experimental verification of clustering of WPPs

with frequency variation was carried out, which necessitates a voltage source with controlled frequency. The uncontrolled VSC model is anyhow equivalent to a stiff voltage source for the purpose of this study [99]. The frequency signal f, when measured, is sensed by a SRF PLL like that described in [128] and used for all simulations in this study. The frequency signal provided to the CC is measured by the PLL implemented in the WTG converter controller.

CC

As emphasised above and in Figure 93, the CC is performing a simple open-loop dispatch of the power reference signals. The output power references must be sent to either the user-built WPPC 1 or the commercial WPPC 2. As will be further discussed below, there are a few significant differences between the two controllers:

 The dynamic performance, depending on the control parameters.

 The position of the POD control signal – see Section 8.3.3.

 The availability of frequency control capability – see Sections 8.3.3 and Appendix 6.

As a consequence, the CC should provide the possibility to make up for such differences in order to achieve the desired coordinated response. This is done by selectors and compensation blocks.

Moreover, the possibility to derive the POD control signals from a frequency variation is also provided by the CC and could be applied e.g. in VSC-HVDC connected WPPs. The generic block diagram of the proposed CC is reported in Figure 95. The model in PowerFactory was coded in DSL for convenience.

Figure 95 - Cluster controller block diagram – only active power path.

The output signals Pref1, Pref2, PrefPOD1 and PrefPOD2 are sent to WPPC 1 and WPPC 2 respectively.

Actually, WPPC 2 can only receive the signal Pref2, since it does not feed-forward the POD signal PrefPOD2. Gains, flags and time constants settings depend on the particular test and whether the output signals are directed to WPPC 1 or WPPC 2. The dispatch is performed with simple gain blocks, but more sensible strategies may be used in real applications, such as for example based on the actual available power of each WPP.

8.3.3 Wind power plant controllers

(a) WPPC 1

The WPPC 1 model was described in Chapter 3 (Figure 14) and is not repeated here. Its implementation is an augmented version of that outlined in the draft IEC standard 61400-27-1 [22] Annex D. The only significant difference with such IEC standard is the possibility to feed-forward the input POD signal, so as to bypass the PI controller and obtain a faster and more robust response. Together with the feed-forward, a freezing algorithm was developed according to Figure 84. It serves to freeze power reference and PI controller output when a POD event is detected.

For convenience, the model has been coded with DSL in PowerFactory. Default parameters for the model are reported in Appendix 6 in Table 37.

(b) WPPC 2

The WPPC 2 model was directly derived from the draft IEC standard 61400-27-1 [22] Annex D and is shown in Figure 96. As can be seen, the main difference from WPPC 1 developed in this study lies in the absence of feed-forward of the POD signal. According to the standard, apart from being provided with frequency and PI controllers, ramp rate limitations are imposed on reference input and reference output and integrator state. The output and integrator state are also limited in modulus between minimum and maximum value. A zero-pole block is placed before the output:

by properly setting its parameters (first order Padé approximation), it can be used to emulate the delays related to the plant controller (e.g. output dispatcher function).

1

-Figure 96 - WPPC 2 active power control block diagram.

The model was coded in DSL with PowerFactory. The parameters for the model and experiments are reported in Appendix 6. It should be mentioned once again that WPPC 2’s frequency control functionality is deactivated at the test facility, since the unit does not have to comply with strict connection regulation and has never been used for this kind of tests before.

Experimental verification of clustering of WPPs

8.3.4 Wind turbine generators

The WTG models are purely based on the draft IEC standard 61400-27-1 models [22], as follows:

 WTG 1 is modelled by a Type 4A model, owing to the fact that no shaft resonances were noticed during previous measurement campaigns on the grid side active power production, since there is no large rotor inertia in the machine driven by the dynamometer.

 WTG 2 is modelled by a Type 4B kind of model, since this kind of machine usually presents shaft resonances. However, it should be noticed that the available sample rate of the power production – see Section 8.2 – may not allow for clear visualisation of the shaft torsional mode. Furthermore, no measurement with WTG 2 operating alone and able to clearly excite the shaft mode was performed and the dominant dynamics in the available measurements are certainly related to WPPC 2. As a consequence, a Type 4A model may be suitable too for the scope of this study. Type 4B is anyhow chosen to have a more realistic platform for possible future usage of the models.

The block diagrams of the models are not reported here, but the reader can refer to [22] for more details. The models’ active power control parameters are reported in Appendix 6. It should be noticed that the main parameters for WTG 1 are very reliable, as they stem from the validation in Section 8.4.2. However, the parameters for WTG 2 are plausible parameters but cannot be considered fully accurate, since the WTG model was not validated in stand-alone. Since the main dynamics that can be observed in the tests conducted in this chapter are certainly related to WPPC 2, small variations in WTG 2’s parameters do not affect the test results significantly.

8.3.5 Communication delays

Communication delays are simply modelled as perfect lumped delays, which in the Laplace domain are expressed by e^-sTdi, with Tdi being the time delay of communication block i. The great difference between the communication channels is in the position of the communication channel and in the value of Tdi, as stated previously and evidenced by Figure 93. In the case of communication between WPPC 1 and WTG 1, the sample rate of both loops is 10 ms, and they are synchronised through SCRAMNet clock within 1 ms. Totally different is the situation for the communication between CC and WPPC 2, which happens asynchronously every 1 s, meaning that the actual delay can fall in the interval 1-2 s.

8.3.6 Implementation

The only blocks actually implemented for conducting the present tests were CC and WPPC 1. A simplified functional sketch of the implementation is shown in Figure 97. The controllers were coded with LabView graphic language operating with continuous time (Laplace domain) blocks.

The main loop and communication loops are running in parallel and communicating between them through shared variables. The Modbus communication loop also performs the necessary discretisation to comply with the input format in WPPC 2 – see Table 34 in Appendix 6.

Initialisation and termination loops are executed once at the beginning and end of the test respectively, in order to properly take initial control and most safely hand the control back to the default controllers once the test is finished.

The Modbus communication loop was also used in stand-alone for some of the tests, in order to manually change the power reference of WPPC 2.

Discretisation and communication

loop Modbus Initialisation

Main loop

Termination

Communication loop SCRAMNet

10 ms 10 ms

1 s

Cluster Controller WPPC 1

Figure 97 - Functional sketch of implementation on PXI.