Modes of Analysis

S1 R1 S2 R2

φ

S3

S4

R3

R4

S5 R5 S6 R6

φ ^S7

S8

R7 R8 A

A A ns ps ns ps

B ns ns ps ps

A A A Anr

pr nr pr

B B B Bnr

pr nr pr B A

B B

F Fⁿ

p n p F /F / /

/

/ /

/ /

/ /

/

Figure 3.4: Completed CRL NAND gate with pipelining support.

that all the output wires are actively driven at the end of the SETting swing and therefore provide for periodic refreshing of the voltages on the oating nodes.

So far, our CRL gate asymptotically requires eight times as many devices as conventional CMOS as illustrated by the 2-input AND/NAND gate example. For circuits that require complementary outputs, such as address decoders, the redundancy factor may be somewhat less.

φ

φ

S1 R1 S2 R2 S3

S4

R3

R4

S5 R5 S6 R6 S7

S8

R7 R8 A

A A ns ps ns ps

B ns ns ps ps

A A A A^nr

pr nr pr

B B B B^nr

pr nr pr B A

B B

F Fⁿ

p n p F F / / /

/

/ /

/ /

/ /

/

T1

T3 Vdd

T2

T4

Vss Clamps

Figure 3.5: First CRL implementation with output cross-coupled clamps.

φ

1

φ

1

φ φ

2

φ 2 R

Q

F

S

n n

(b) (a)

/ /

Figure 3.6: (a) CRL abstraction box. (b) Timing of the four clock rails.

the top rail is connected to

¹ and the bottom rail to

=

¹, while a clock of

=

¹ indicates that the top rail is connected to

=

¹ and the bottom rail to

¹.

Using this abstraction, Figure 3.7 illustrates how CRL gates are connected to produce a non-dissipative pipeline. The timing of the four clock lines is shown in Figure 3.6b. Note that the box with a function

F

^;1 performs the inverse operation of the box with a function

F

. To SET a box, all the SET inputs must be valid and stable and all the RESET inputs must be idle, i.e., they come from a box that is currently in RESET, so that all the RESET pass gates are OFF. With these inputs, swinging the clock rails of the box away from their rest level will SET the box. To RESET the box, the rails are returned to their rest levels while the SET inputs are idle and the RESET inputs are active and stable.

a₀

R φ

Q

F

S

F

S

Q R 1

1 1

−1

R φ

Q

F

S

F

S

Q R 2

2 2

−1

R φ

Q

F

S

F

S

Q R 3

3 1

−1

R φ

Q

F

S

F

S

Q R

−1 2 4

4

R φ

Q

F

S

F

S

Q R 1

φ1 φ

φ 2

2 φ

1 φ

2 −1 5

5

/ /

/ /

Figure 3.7: Non-dissipative multi-stage pipeline connection.

To follow the operation of the circuit we start with

¹ and

² at their rest state and assume that the pipeline has been operating for some time. We follow the propagation of the input

a

⁰ only, even though other parallel activity is going on. From the states of the clocks we see that box

F

¹ is RESET and its RESET inputs are idle as well. Swinging

¹ SETs

F

¹ and computes

F

¹(

a

⁰). Swinging

² now SETs

F

² and

F

^1;1 and produces

F

²(

F

¹(

a

⁰)) and

F

^1;1(

F

¹(

a

⁰)) =

a

⁰ respectively. Now swinging

¹ to its rest level RESETs

F

¹, produces

F

³(

F

²(

F

¹(

a

⁰))) and

F

^2;1(

F

²(

F

¹(

a

⁰))) =

F

¹(

a

⁰). The circuit is now ready to safely RESET boxes

F

² and

F

^1;1. One can see that we can continuously drive a new input into the network every

¹ and successfully operate the pipeline in a non-dissipative fashion. In addition, this pipeline can have any arbitrary number of stages and still be driven entirely by

¹,

² and their inverses only.

There remains one problem however. At the end of the pipeline the RESET input to

F

^5;1 is not available and hence resetting this box is dissipative. Furthermore, it could not be generated, as this is the place where reversibility is broken. We can however, restore reversibility here through brute force by connecting to the end of this pipeline a mirror, and an inverse, image of itself. The missing input at the end of this extended pipeline that is needed to reverse the last inverse box is now simply

a

⁰. With this topology, we can proceed without any dissipation by continually supplying delayed copies of the input to the pipeline at the inverse input on the far right. The technique of connecting an inverse network to the forward network was previously used in [13] and [11] to eliminate dissipation through recycling the intermediate garbage that results in conservative logic.

Admittedly, the above solution is more of theoretical than practical interest. If re-versibility needs to be broken, that is, when information loss cannot be avoided, then some dissipation will occur for every lost bit of information. For these situations, we can reduce the dissipation by ending the pipeline with two identity boxes,

I

(

a

) =

a

, and use the out-put of the lower identity box to reset itself as shown in Figure 3.8. Closer examination shows that the dissipation is ¹²

CV

_T² per bit per cycle as opposed to ¹²

CV

_dd² for conventional gates. Since the output of an identity box is the same as the input, the resetting swing proceeds normally until the output levels are insucient to keep the appropriate pass gates on. Because of this, some internal nodes will have a potential that is one

V

T away from their reset levels. The next input to the gate will short this potential dierence resulting in ¹²

CV

_T² dissipation per bit. Note that that we only pay this penalty at the last stage of a long pipeline.

R φ

Q

F

S

F

S

Q R

φ

R φ

Q S

S

Q R

φ

2 1

2 1 −1

I I

n n/

Figure 3.8: Last pipeline stage connection for dissipation reduction.

In document A viable systems analysis of development control services in English Local Planning Authorities (Page 120-133)